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NanoBridge Technology for Embedded Novolatile Memory Application 纳米桥技术在嵌入式非易失性存储器中的应用
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779309
Munehiro Tada
{"title":"NanoBridge Technology for Embedded Novolatile Memory Application","authors":"Munehiro Tada","doi":"10.1109/IMW52921.2022.9779309","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779309","url":null,"abstract":"NanoBridge (NB) is a kind of electrochemical resistive-change device using Cu ion migration from Cu interconnects into electrolyte. NBs are integrated by only two additional masks in a standard Cu-BEOL without scarifying CMOS performance. The newly developed split Cu electrode enables the lower set voltage (2.2V) and superior retention, which have been demonstrated in a 28 nm-node. High density embedded nonvolatile NB memory macro in a 65nm technology is successfully developed with $mathrm{P}/mathrm{E}=30text{ns}/30text{ns}$ programming based on the highly reliable and low-cost manufacturable NB technology. High yield is achieved with satisfying 30ns read, and more than 10 years retention at 150°C. NB properties can be systematically adjusted by tailoring the NB stack, achieving to broaden NB applications.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction 用于3D NAND编程降低电压的高k离子隧道层
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779307
L. Breuil, L. Nyns, S. Rachidi, K. Banerjee, A. Arreghini, J. Bastos, S. Ramesh, G. V. D. Bosch, M. Rosmeulen
{"title":"High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction","authors":"L. Breuil, L. Nyns, S. Rachidi, K. Banerjee, A. Arreghini, J. Bastos, S. Ramesh, G. V. D. Bosch, M. Rosmeulen","doi":"10.1109/IMW52921.2022.9779307","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779307","url":null,"abstract":"In this paper, we develop a SiON layer with High-K incorporated (HKSiON) for tunnel oxide in a 3D-NAND gate stack. The objective is to improve the programming efficiency that tends to degrade with Z-pitch scaling, as well as with a possible transition from Gate All Around to Trench cells architecture. The results show that increasing the High-K content in a SiON tunnel layer leads to a significant reduction in programming voltage at the expense of retention, therefore causing a trade-off between these two parameters. Low High-K content however, can bring a distinct improvement in programming with limited retention penalty only.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126418885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multilayer Deposition in Phase-Change Memory for Best Endurance Performance and Reduced Bit Error Rate 相变存储器中的多层沉积可获得最佳持久性能和降低误码率
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779285
Gemma Navarro, C. Sabbione, V. Meli, L. Nistor, M. Frei, J. Garrione, M. Tessaire, F. Fillot, N. Bernier, E. Nolot, B. Sklénard, J. Li, S. Martin, N. Castellani, G. Bourgeois, M. Cyrille, F. Andrieu
{"title":"Multilayer Deposition in Phase-Change Memory for Best Endurance Performance and Reduced Bit Error Rate","authors":"Gemma Navarro, C. Sabbione, V. Meli, L. Nistor, M. Frei, J. Garrione, M. Tessaire, F. Fillot, N. Bernier, E. Nolot, B. Sklénard, J. Li, S. Martin, N. Castellani, G. Bourgeois, M. Cyrille, F. Andrieu","doi":"10.1109/IMW52921.2022.9779285","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779285","url":null,"abstract":"In this work we investigate the benefits of amorphous Multilayer (ML) deposition in Phase-Change Memory (PCM). Different ML stacks based on Ge1 Sb2 Te4 composition are developed and characterized by physico-chemical analyses, providing a spectacular demonstration of highly-textured crystalline layer after high thermal budget and of higher layer uniformity. ML PCM device performances are evaluated at statistical level in 16 kb arrays, showing a lower electrical parameters variability, best endurance results and lowest Bit Error Rate wrt equivalent bulk layer.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121127343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Spin-Transfer-Torque MRAM: the Next Revolution in Memory 自旋-传递-扭矩MRAM:存储器的下一次革命
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779288
D. Worledge
{"title":"Spin-Transfer-Torque MRAM: the Next Revolution in Memory","authors":"D. Worledge","doi":"10.1109/IMW52921.2022.9779288","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779288","url":null,"abstract":"This paper introduces the operation and features of Spin-Transfer-Torque Magnetoresistive Random Access Memory (STT-MRAM), and provides a brief history of the field. Then the four main applications of STT-MRAM are described. A review is given of the initial demonstration of perpendicular STT-MRAM and the subsequent development of this technology at IBM. Finally, several potential paths forward to more advanced applications are described.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128111431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges 基于铁电场效应管的多能级NVM存储窗口扩展:极化与注入电荷相结合的混合解决方案
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779292
Jae-Gil Lee, Joong-Kwon Kim, D. Suh, Ildo Kim, G. D. Han, S. Ryu, Seho Lee, M. Na, Seonyong Cha, H. Park, C. S. Hwang
{"title":"Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges","authors":"Jae-Gil Lee, Joong-Kwon Kim, D. Suh, Ildo Kim, G. D. Han, S. Ryu, Seho Lee, M. Na, Seonyong Cha, H. Park, C. S. Hwang","doi":"10.1109/IMW52921.2022.9779292","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779292","url":null,"abstract":"The memory window (MW) of a metal-ferroelectric-semiconductor (MFS)-based ferroelectric field-effect transistor (FE-FET) is generally 2Vc, where Vc is the coercive voltage of the FE layer. When applying the program and erase voltages, adverse charge injection from the gate metal or the channel likely occurs. While the latter decreases the MW, the former may further increase it over 2Vc, which is highly useful for the multilevel FE-FET. In this work, we propose a metal-insulator-ferroelectric-semiconductor (MIFS)-based FE-FET to widen the MW by providing additional charges at the gate metal/ferroelectric interface. When part of the injected charges are retained at the polarization switching, the Vc increases, and thus, MW also increases. This is due to the additional voltage drop by the injected charge exchange at the moment of FE switching. For a given FE layer thickness, the MW of MIFS-stacked FE-FET was expanded by ∼55% compared to MFS-stacked FE-FET.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121633489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Recognition Accuracy Enhancement using Interface Control with Weight Variation-Lowering in Analog Computation-in-Memory 内存模拟计算中减小权值变化的接口控制提高识别精度
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779296
S. Park, Gyonhui Lee, Youngjae Kwon, D. Suh, Hanwool Lee, Sangeun Je, Dabin Kim, Dohan Lee, Seungwook Ryu, Seungbum Kim, Euiseok Kim, Sunghoon Lee, Kyoung Park, Seho Lee, Myung-Hee Na, Seonyong Cha
{"title":"Recognition Accuracy Enhancement using Interface Control with Weight Variation-Lowering in Analog Computation-in-Memory","authors":"S. Park, Gyonhui Lee, Youngjae Kwon, D. Suh, Hanwool Lee, Sangeun Je, Dabin Kim, Dohan Lee, Seungwook Ryu, Seungbum Kim, Euiseok Kim, Sunghoon Lee, Kyoung Park, Seho Lee, Myung-Hee Na, Seonyong Cha","doi":"10.1109/IMW52921.2022.9779296","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779296","url":null,"abstract":"As AI technology develops, it is necessary to verify the technical feasibility of Memory-Centric convergence technology. Previously investigated resistive synaptic devices (RSDs) can successfully mimic the function of biological synapses. However, the effect of the system recognition rate reflecting the variation of 16 weight states has not been studied yet. In this article, we perform simulations of various weight variation sets through real resistive synaptic device (RSD) engineering in Analog Computation-in-Memory (ACiM) system. These simulation results can provide guidelines for the continued design and optimization of a resistive synaptic device for realizing ACiM.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124751810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High temperature stability embedded ReRAM for 2x nm node and beyond 高温稳定性嵌入式ReRAM 2x nm节点及以上
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779293
G. Molas, G. Piccolboni, A. Bricalli, A. Verdy, I. Naot, Y. Cohen, A. Regev, I. Naveh, D. Deleruyelle, Q. Rafhay, N. Castellani, L. Reganaz, A. Persico, R. Segaud, J. Nodin, V. Meli, S. Martin, F. Andrieu, L. Grenouillet
{"title":"High temperature stability embedded ReRAM for 2x nm node and beyond","authors":"G. Molas, G. Piccolboni, A. Bricalli, A. Verdy, I. Naot, Y. Cohen, A. Regev, I. Naveh, D. Deleruyelle, Q. Rafhay, N. Castellani, L. Reganaz, A. Persico, R. Segaud, J. Nodin, V. Meli, S. Martin, F. Andrieu, L. Grenouillet","doi":"10.1109/IMW52921.2022.9779293","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779293","url":null,"abstract":"We report the performances and reliability of our ReRAM technology integrated in 28nm node. Low raw BER approaching 10−5 without ECC or redundancy is achieved. 106 cycles endurance without significant window degradation is shown. We report stable memory window after 15h bake at 210°C after 10kcycles, which is one of the best results reported so far to our knowledge. Technology passed basic (3x reflow) and extended (9 cycles) SMT tests with zero failures. Bitcell and memory stack engineering improved the window margin statistics. Optimized forming protocols are developed to increase memory yield over cycling. Program and verify algorithms allowed to insure no overlap between high and low resistive states on 1Mb arrays.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129913956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Racetrack Memory: a high capacity, high performance, non-volatile spintronic memory 赛马场存储器:一种高容量、高性能、非易失性的自旋电子存储器
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779286
S. Parkin
{"title":"Racetrack Memory: a high capacity, high performance, non-volatile spintronic memory","authors":"S. Parkin","doi":"10.1109/IMW52921.2022.9779286","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779286","url":null,"abstract":"Racetrack Memory is a novel, emerging spintronic memory whose fundamental principle is the movement of the encoded digital data, in the form of chiral magnetic domain walls, along nanoscopic magnetic racetracks, to reading and writing devices that are built into the racetrack itself. Thus, a single device - the racetrack - accommodates multiple bits, perhaps as many as one hundred or more, thereby allowing for massive data capacities that rival those of magnetic disk drives or today's solid-state memories. The domain walls are moved by nanosecond current pulses that are converted into spin-polarized currents via volume spin dependent scattering, or into pure spin currents via spin-orbit coupling derived phenomena, most importantly the spin Hall effect. Recent discoveries that have shown highly efficient current induced motion of chiral domain walls with speeds of ∼1 km/s or higher in synthetic antiferromagnetic racetracks make possible high performance racetrack memories. Of special interest is a one-domain wall racetrack memory that has the potential to operate at deep sub-nanosecond speeds, and, thereby, could supplant SRAM and, moreover, be much denser than today's or prospective SRAM and, in addition, is non-volatile. There is no other memory technology that has the enormous potential of Racetrack Memory.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121185777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bi-directional read method to reduce SOT-specific read disturbance for highly reliable SOT-MRAM 双向读取方法减少高可靠性SOT-MRAM的sot特异性读取干扰
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/IMW52921.2022.9779297
Akihiro Yamada, Yuwa Kishi, T. Kawahara
{"title":"Bi-directional read method to reduce SOT-specific read disturbance for highly reliable SOT-MRAM","authors":"Akihiro Yamada, Yuwa Kishi, T. Kawahara","doi":"10.1109/IMW52921.2022.9779297","DOIUrl":"https://doi.org/10.1109/IMW52921.2022.9779297","url":null,"abstract":"We propose a bi-directional read method for improving read-disturbing resistance to maintain high read reliability of spin-orbit-torque magnetoresistive random-access memory. Since this method can withstand magnetization switching with a current 10 times or more that of the conventional method, it enables low power consumption operation while maintaining high read reliability. We evaluated our method in terms of improving read disturbance resistance by focusing on, the dependence of material properties, size, and wiring resistance in the memory cell array. We also evaluated the read reliability as a chip to confirm the method's effectiveness.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"4 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132193839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IMW 2022 Sponsors IMW 2022赞助商
2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI: 10.1109/imw52921.2022.9779302
{"title":"IMW 2022 Sponsors","authors":"","doi":"10.1109/imw52921.2022.9779302","DOIUrl":"https://doi.org/10.1109/imw52921.2022.9779302","url":null,"abstract":"","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133676450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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