用于3D NAND编程降低电压的高k离子隧道层

2022 IEEE International Memory Workshop (IMW) Pub Date : 2022-05-01 DOI:10.1109/IMW52921.2022.9779307

L. Breuil, L. Nyns, S. Rachidi, K. Banerjee, A. Arreghini, J. Bastos, S. Ramesh, G. V. D. Bosch, M. Rosmeulen

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引用次数: 1

摘要

在本文中，我们开发了一种用于隧道氧化物的高钾离子层(HKSiON)，用于3D-NAND栅极堆叠。目标是提高编程效率，因为编程效率往往会随着Z-pitch缩放而降低，同时也可能从Gate All Around过渡到Trench单元结构。结果表明，增加隧道层中High-K含量会导致编程电压的显著降低，但代价是保留，因此导致这两个参数之间的权衡。然而，低-高-钾含量可以带来编程方面的明显改进，而且只会带来有限的保留损失。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction

In this paper, we develop a SiON layer with High-K incorporated (HKSiON) for tunnel oxide in a 3D-NAND gate stack. The objective is to improve the programming efficiency that tends to degrade with Z-pitch scaling, as well as with a possible transition from Gate All Around to Trench cells architecture. The results show that increasing the High-K content in a SiON tunnel layer leads to a significant reduction in programming voltage at the expense of retention, therefore causing a trade-off between these two parameters. Low High-K content however, can bring a distinct improvement in programming with limited retention penalty only.

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2022 IEEE International Memory Workshop (IMW)

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