G. Molas, G. Piccolboni, A. Bricalli, A. Verdy, I. Naot, Y. Cohen, A. Regev, I. Naveh, D. Deleruyelle, Q. Rafhay, N. Castellani, L. Reganaz, A. Persico, R. Segaud, J. Nodin, V. Meli, S. Martin, F. Andrieu, L. Grenouillet
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引用次数: 2
Abstract
We report the performances and reliability of our ReRAM technology integrated in 28nm node. Low raw BER approaching 10−5 without ECC or redundancy is achieved. 106 cycles endurance without significant window degradation is shown. We report stable memory window after 15h bake at 210°C after 10kcycles, which is one of the best results reported so far to our knowledge. Technology passed basic (3x reflow) and extended (9 cycles) SMT tests with zero failures. Bitcell and memory stack engineering improved the window margin statistics. Optimized forming protocols are developed to increase memory yield over cycling. Program and verify algorithms allowed to insure no overlap between high and low resistive states on 1Mb arrays.
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