一种新颖的3D 1T1R RRAM架构,用于以内存为中心的超维计算

T. Dubreuil, P. Amari, S. Barraud, J. Lacord, E. Esmanhotto, V. Meli, S. Martin, N. Castellani, B. Previtali, François Andrieu
{"title":"一种新颖的3D 1T1R RRAM架构,用于以内存为中心的超维计算","authors":"T. Dubreuil, P. Amari, S. Barraud, J. Lacord, E. Esmanhotto, V. Meli, S. Martin, N. Castellani, B. Previtali, François Andrieu","doi":"10.1109/IMW52921.2022.9779306","DOIUrl":null,"url":null,"abstract":"In this work, we present a novel 3D 1T1R RRAM architecture. Thanks to a proper connection of SourceLines (SLs), BitLines (BLs), and WordLines (WLs), we propose to implement a memory-centric hyperdimensional computing (HDC) algorithm for language recognition. SPICE simulations validate the main HD vector operations (i.e generation of seed hypervectors, XNOR, SHIFT, etc.) with an efficiency reaching up to 95%. On this basis, we demonstrated a first experimental implementation of AND operation with a 1kb RRAM array. Finally, we discuss how each part of this 3D structure integrates and links each building block of HDC algorithm with a high level of parallelism.","PeriodicalId":132074,"journal":{"name":"2022 IEEE International Memory Workshop (IMW)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing\",\"authors\":\"T. Dubreuil, P. Amari, S. Barraud, J. Lacord, E. Esmanhotto, V. Meli, S. Martin, N. Castellani, B. Previtali, François Andrieu\",\"doi\":\"10.1109/IMW52921.2022.9779306\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we present a novel 3D 1T1R RRAM architecture. Thanks to a proper connection of SourceLines (SLs), BitLines (BLs), and WordLines (WLs), we propose to implement a memory-centric hyperdimensional computing (HDC) algorithm for language recognition. SPICE simulations validate the main HD vector operations (i.e generation of seed hypervectors, XNOR, SHIFT, etc.) with an efficiency reaching up to 95%. On this basis, we demonstrated a first experimental implementation of AND operation with a 1kb RRAM array. Finally, we discuss how each part of this 3D structure integrates and links each building block of HDC algorithm with a high level of parallelism.\",\"PeriodicalId\":132074,\"journal\":{\"name\":\"2022 IEEE International Memory Workshop (IMW)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Memory Workshop (IMW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW52921.2022.9779306\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW52921.2022.9779306","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

在这项工作中,我们提出了一种新颖的3D 1T1R RRAM架构。通过对源线(SLs)、位线(BLs)和词线(wl)的适当连接,我们提出了一种以内存为中心的语言识别超维计算(HDC)算法。SPICE仿真验证了主要的高清矢量操作(即生成种子超矢量、XNOR、SHIFT等),效率高达95%。在此基础上,我们演示了使用1kb RRAM阵列进行AND操作的第一个实验实现。最后,我们讨论了该3D结构的每个部分如何以高并行度集成和链接HDC算法的每个构建块。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing
In this work, we present a novel 3D 1T1R RRAM architecture. Thanks to a proper connection of SourceLines (SLs), BitLines (BLs), and WordLines (WLs), we propose to implement a memory-centric hyperdimensional computing (HDC) algorithm for language recognition. SPICE simulations validate the main HD vector operations (i.e generation of seed hypervectors, XNOR, SHIFT, etc.) with an efficiency reaching up to 95%. On this basis, we demonstrated a first experimental implementation of AND operation with a 1kb RRAM array. Finally, we discuss how each part of this 3D structure integrates and links each building block of HDC algorithm with a high level of parallelism.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信