A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing

Abstract

In this work, we present a novel 3D 1T1R RRAM architecture. Thanks to a proper connection of SourceLines (SLs), BitLines (BLs), and WordLines (WLs), we propose to implement a memory-centric hyperdimensional computing (HDC) algorithm for language recognition. SPICE simulations validate the main HD vector operations (i.e generation of seed hypervectors, XNOR, SHIFT, etc.) with an efficiency reaching up to 95%. On this basis, we demonstrated a first experimental implementation of AND operation with a 1kb RRAM array. Finally, we discuss how each part of this 3D structure integrates and links each building block of HDC algorithm with a high level of parallelism.