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2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)最新文献

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An electrical study of USB2.0 channels supporting multiplexers/BC1.2 power switches/charging modules 支持多路复用器/BC1.2电源开关/充电模块的USB2.0通道的电学研究
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347137
Tan Wei Jern, Tiang Bih Qui
{"title":"An electrical study of USB2.0 channels supporting multiplexers/BC1.2 power switches/charging modules","authors":"Tan Wei Jern, Tiang Bih Qui","doi":"10.1109/EPEPS.2015.7347137","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347137","url":null,"abstract":"An electrical study on USB2.0 channels supporting multiplexers, BC1.2 power switches and charging modules is presented in this paper. The issues caused by the inclusion of the aforementioned devices in a USB2.0 channel are tackled in the key learnings of this paper. The proposed methods focus on channel design on existing and new signaling. Of note, they maintain design flexibility, while maintaining healthy compliance eye margins. The methods primarily mitigate harmful signal degradation through correct device placement in the channel, tradeoff between device loss and length in mainstream, tablet and phone solutions. Ultimately, this translates into a shift in line with recent platforms' move to extend the usage of the USB2.0 interface into a wider number of applications.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116067775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and signal integrity analysis of high bandwidth memory (HBM) interposer in 2.5D terabyte/s bandwidth graphics module 2.5D tb /s带宽图形模块中高带宽存储器(HBM)插播器的设计与信号完整性分析
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347149
Hyunsuk Lee, Kyungjun Cho, Heegon Kim, Sumin Choi, Jaemin Lim, H. Shim, Joungho Kim
{"title":"Design and signal integrity analysis of high bandwidth memory (HBM) interposer in 2.5D terabyte/s bandwidth graphics module","authors":"Hyunsuk Lee, Kyungjun Cho, Heegon Kim, Sumin Choi, Jaemin Lim, H. Shim, Joungho Kim","doi":"10.1109/EPEPS.2015.7347149","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347149","url":null,"abstract":"Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125186160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A prediction method of heat generation in the silicon substrate for 3-D ICs 三维集成电路硅衬底产热的预测方法
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347136
Yi-An Hsu, Chi-Hsuan Cheng, Tzong-Lin Wu, Yi-Chang Lu
{"title":"A prediction method of heat generation in the silicon substrate for 3-D ICs","authors":"Yi-An Hsu, Chi-Hsuan Cheng, Tzong-Lin Wu, Yi-Chang Lu","doi":"10.1109/EPEPS.2015.7347136","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347136","url":null,"abstract":"Through-silicon via (TSV) based 3-D ICs provide a promising solution for miniaturizing chips. However, thermal issue in 3-D ICs cannot be ignored. In this paper, we proposed a method based on 3-D transmission line matrix (3-D TLM) method to calculate heat generation in the lossy silicon substrate caused by TSV induced electrical field. Pseudo random bit sequences (PRBS) at different bit rates are fed into TSVs to simulate the transmitted digital signal. The influence of TSV arrangements and TSV oxide thickness to the heat generation are also investigated in time-domain. With the help of this method, the generation and distribution of heat in the silicon substrate can be predicted.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115280472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An electromagnetic model for back-drilled vias 后钻过孔的电磁模型
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347127
A. Rong, A. Cangellaris, Feng Ling
{"title":"An electromagnetic model for back-drilled vias","authors":"A. Rong, A. Cangellaris, Feng Ling","doi":"10.1109/EPEPS.2015.7347127","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347127","url":null,"abstract":"The Foldy-Lax formulation for the electromagnetic modeling of planar, multilayered substrates with multiple pins and vias is extended to include the presence of back-drilled via holes. A validation study of the accuracy of the proposed model is also presented.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114278032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Broadband material model identification with GMS-parameters 基于gms参数的宽带材料模型识别
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347151
Y. Shlepnev
{"title":"Broadband material model identification with GMS-parameters","authors":"Y. Shlepnev","doi":"10.1109/EPEPS.2015.7347151","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347151","url":null,"abstract":"Design and compliance analysis of PCB and packaging interconnects for 10-50 Gbps and higher data rates should begin with the identification of broadband dielectric and conductor roughness models. Such models are not available from manufacturers and the model identification is the most important element of successful interconnect design. Broadband model identification with generalized modal S-parameters (GMS-parameters) is outlined and compared with the standardized Short Pulse Propagation (SPP) technique. Practical examples of successful dielectric and conductor roughness model identification up to 50 GHz are also provided.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A study of conductor modeling using the surface integral equation 导体表面积分方程建模的研究
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347146
T. Xia, H. Gan, M. Wei, W. Chew
{"title":"A study of conductor modeling using the surface integral equation","authors":"T. Xia, H. Gan, M. Wei, W. Chew","doi":"10.1109/EPEPS.2015.7347146","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347146","url":null,"abstract":"A rigorous method to solve conductor problems using the surface integral equation is introduced. This formulation is based on the augmented electric field integral equation. In order to model conductors and accurately capture the losses, some integration techniques are analyzed and compared. The line integral method will be an optimal option for conductor problems. After incorporating this technique, this method can be applied to interconnect and packaging problems.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124503661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges of high-speed channel design on GPU accelerated system GPU加速系统中高速通道设计的挑战
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347166
Chun-Lin Liao, Terence Rodrigues, B. Mutnury
{"title":"Challenges of high-speed channel design on GPU accelerated system","authors":"Chun-Lin Liao, Terence Rodrigues, B. Mutnury","doi":"10.1109/EPEPS.2015.7347166","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347166","url":null,"abstract":"High speed servers continue to deploy graphics processing units (GPUs) in them for large volume data computation. Robustness of signal integrity on the high-speed channel is an important factor in these high performance computing (HPC) system designs. In this paper, the simulation and validation / debugging procedure of a 1U / 2 socket rack server that can support up to 4 GPU units was used as exampled to investigate the challenges on such high-speed channel design.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132082196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-speed serial link challenges using multi-level signaling 高速串行链路挑战使用多级信令
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347129
N. Dikhaminjia, J. He, E. Hernandez, M. Tsiklauri, J. Drewniak, A. Chada, M. Zvonkin, B. Mutnury
{"title":"High-speed serial link challenges using multi-level signaling","authors":"N. Dikhaminjia, J. He, E. Hernandez, M. Tsiklauri, J. Drewniak, A. Chada, M. Zvonkin, B. Mutnury","doi":"10.1109/EPEPS.2015.7347129","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347129","url":null,"abstract":"The paper discusses challenges of high-speed serial links using multi-level signaling and gives comparison of the performance of the various channels with different lossy materials and equalization options. Advantages and problems of multi-level signaling are shown based on the test results.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134182806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
IBIS-AMI modelling of high-speed memory interfaces 高速存储器接口的IBIS-AMI建模
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347132
John Yan, Arash Zargaran-Yazd
{"title":"IBIS-AMI modelling of high-speed memory interfaces","authors":"John Yan, Arash Zargaran-Yazd","doi":"10.1109/EPEPS.2015.7347132","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347132","url":null,"abstract":"This paper presents techniques to accelerate the exploration of advanced memory links through IBIS-AMI modelling of the transmitter and receiver. The results show over 1000× CPU time speed improvement compared to full transistor level SPICE simulations while providing a fair representation of the interface performance. To demonstrate the versatility the IBIS-AMI for memory interfaces, data transmission at 2.4 Gbps and 6.4 Gbps, over the same multidrop channel with different equalization features, are presented.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126631004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Crosstalk reduction by matrix matching 矩阵匹配的串扰抑制
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI: 10.1109/EPEPS.2015.7347163
H. Braunisch, A. Elsherbini
{"title":"Crosstalk reduction by matrix matching","authors":"H. Braunisch, A. Elsherbini","doi":"10.1109/EPEPS.2015.7347163","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347163","url":null,"abstract":"Based on the recognition that propagating near-end crosstalk is the primary source of crosstalk noise in short unterminated channels we describe and demonstrate an approach to improve the signal integrity on such channels significantly. The basic physics and Norton formulation of crosstalk reduction by matrix matching are described. We then show large potential gains for two on-package interconnect application examples. A nominal strip line configuration based on standard package design rules and including realistic modeling assumptions yields 50.4% reduced channel power at iso-performance. The same design can be converted to microstrip without degrading eye height and channel power.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125300791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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