Challenges of high-speed channel design on GPU accelerated system

Abstract

High speed servers continue to deploy graphics processing units (GPUs) in them for large volume data computation. Robustness of signal integrity on the high-speed channel is an important factor in these high performance computing (HPC) system designs. In this paper, the simulation and validation / debugging procedure of a 1U / 2 socket rack server that can support up to 4 GPU units was used as exampled to investigate the challenges on such high-speed channel design.