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2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)最新文献

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Hierarchical modeling and scalable algorithms for in-situ analysis of integrated circuit packages 集成电路封装现场分析的分层建模和可扩展算法
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874404
Z. Peng, Yang Shao, Shu Wang
{"title":"Hierarchical modeling and scalable algorithms for in-situ analysis of integrated circuit packages","authors":"Z. Peng, Yang Shao, Shu Wang","doi":"10.1109/EDAPS.2016.7874404","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874404","url":null,"abstract":"The objective of this work is to investigate high-resolution and high-performance computational methods for the first-principles analysis of in-situ product-level integrated circuit (IC) packages. The novelties and key technical approaches of the proposed work include: (i) a scalable geometry-based domain decomposition (DD) method to conquer the geometric complexity of physical domain, which leads to quasi-optimal convergence that is provably scalable for multi-scale objects. Moreover, it results in parallel and scalable computational algorithms to reduce the time complexity via high performance computing facilities; (ii) a hierarchical multi-scale simulator for high-definition IC package systems, in which the technical ingredients include a skeleton-based multi-region multi-solver method and a variational macro-micro analysis for multi-scale modeling. The capability and benefits of the algorithms are explored and illustrated through several real-world 3D IC package applications.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128425103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel de-embedding method with Look-Up Table for characterization of interconnects 基于查找表的互连表征去嵌入新方法
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874414
Shaowu Huang, Beomtaek Lee
{"title":"Novel de-embedding method with Look-Up Table for characterization of interconnects","authors":"Shaowu Huang, Beomtaek Lee","doi":"10.1109/EDAPS.2016.7874414","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874414","url":null,"abstract":"A new de-embedding technique is introduced in this paper with pre-established Look-Up Table (LUT) for accurate characterization of high speed interconnects, particularly for printed circuit board (PCB). The method de-embeds the test fixture effects from the measurement or/and simulation results. It improves the accuracy and reduces the PCB layout area comparing to one line method. It reduces the PCB layout area and improves the measurement efficiency comparing to two line method.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125695252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient methodology for modeling structure of high-speed long transmission lines 高速长输电线路结构建模的有效方法
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874421
T. Yu, Jian Chen, Chiawen Shih
{"title":"Efficient methodology for modeling structure of high-speed long transmission lines","authors":"T. Yu, Jian Chen, Chiawen Shih","doi":"10.1109/EDAPS.2016.7874421","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874421","url":null,"abstract":"A practical approach for accurately modeling high-speed link structures is presented and named as the “cut and stitch” (C&S) methodology. To generate S-parameters for the whole system, C&S first cuts the structure into different parts with different electromagnetic (EM) features and also provides auto-generated ports at the cutting interfaces to do system connection later, then selects the proper EM solver for individual design partition's modeling, and finally automatically stitches all of the S-parameter models together. Numerical experiments show that the approach can achieve more than one order of the speedup ratio with the acceptable accuracy.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131070233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast model order reduction of RC networks with very large order and port count 具有非常大的订单和端口数的RC网络的快速模型订单缩减
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874437
Denis Oyaro, P. Triverio
{"title":"Fast model order reduction of RC networks with very large order and port count","authors":"Denis Oyaro, P. Triverio","doi":"10.1109/EDAPS.2016.7874437","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874437","url":null,"abstract":"We present a scalable method for the model order reduction of very large RC circuits. Such circuits arise in the modeling of on-chip power distribution networks. The method achieves moment matching with efficient Householder transformations and sparse matrix factorizations. It preserves passivity and generate sparse, efficient models. It overcomes the limited scalability of standard Krylov methods, that become inefficient beyond a few hundreds of ports. Numerical results demonstrate the superior performance of the proposed method in terms of reduction time and model efficiency. Scalability is demonstrated up to 1.2 million nodes and 2,400 ports.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interconnected capacitors for effective power delivery noise suppression across domains 用于跨域有效功率传递噪声抑制的互连电容器
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874397
Sameer Shekhar, A. Jain
{"title":"Interconnected capacitors for effective power delivery noise suppression across domains","authors":"Sameer Shekhar, A. Jain","doi":"10.1109/EDAPS.2016.7874397","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874397","url":null,"abstract":"Optimal power delivery network design relies on decoupling capacitors that consume significant package and board real estate, which is becoming scarce due to shrinking chip sizes and overall system form factors. This paper addresses noise reduction via capacitor interconnection between different voltage domains to leverage decoupling capacitors across domains. Novel structures that integrate decoupling and interconnection capacitor are then proposed. The complete solution delivers more than 40% noise reduction per unit capacitor area. Simulation results are provided for illustration.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133861888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis and system optimization of high performance clocking for modern mobile platforms 现代移动平台的高性能时钟分析与系统优化
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874444
X. Qi, R. Mittal, S. Ji, S. Puligundla
{"title":"Analysis and system optimization of high performance clocking for modern mobile platforms","authors":"X. Qi, R. Mittal, S. Ji, S. Puligundla","doi":"10.1109/EDAPS.2016.7874444","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874444","url":null,"abstract":"Modern mobile platforms contain mainly active components in a small area with stringent power and cost targets. An integrated clock is needed for PLLs, component internal functions as well as transferring data among them. Due to the small mobile form factors, the noise coupling from power/ground and signals to the integrated clock circuitry becomes more evident impacting clock performance significantly. A method of signal and power integrity analysis and system optimization is proposed to design clocks in System-on-Chip (SoC), package and platform of mobile products such as wearables, phones and tablets. The measured results from high volume mobile systems show 30% clock jitter reduction from generation to generation using the frequency domain analysis and system optimization.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122387616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of CMA evolution strategy to synthesis of multi-resonance spice models up to 20 GHz CMA演化策略在20 GHz多共振spice模型合成中的应用
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874402
I. Kalimulin, A. Zabolotsky, T. Gazizov
{"title":"Application of CMA evolution strategy to synthesis of multi-resonance spice models up to 20 GHz","authors":"I. Kalimulin, A. Zabolotsky, T. Gazizov","doi":"10.1109/EDAPS.2016.7874402","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874402","url":null,"abstract":"A developed method for the macromodels synthesis in the form of an equivalent circuit consisting of RLC elements, using the active covariance matrix adaptation evolution strategy (active CMA-ES), is described. A fitness function taking into account the module and phase of the frequency dependence of reflection or transmission coefficient is described. Two examples of models synthesis for resistor and capacitor according to the measured frequency response, containing several resonances, are given. The developed models have shown good accuracy.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"37 18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Return loss characterization and analysis of high-speed serial interface 高速串行接口回波损耗特性与分析
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874441
W. Beyene, C. Madden, N. Vaidya, H. Lan
{"title":"Return loss characterization and analysis of high-speed serial interface","authors":"W. Beyene, C. Madden, N. Vaidya, H. Lan","doi":"10.1109/EDAPS.2016.7874441","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874441","url":null,"abstract":"This paper describes the return loss characterization and analysis of a high-speed serial interface with T-coils at the transmitter and receiver. Today's high-speed links utilize equalization to mitigate channel loss and dispersion. In addition, T-coil networks are used at inputs and outputs to improve impedance matching and to enhance the receiver and transmitter bandwidth. To guarantee the transceiver performance, a wide range of Serializer Deserializer (SerDes) compliance specifications exist for the return loss measured at or near the package interface and the Printed Circuit Board (PCB). For multi-protocol SerDes, thus, T-coil networks are often necessary to meet the most stringent return loss specification. This paper presents the analysis and characterization of a high-speed transceiver with T-coils designed in a 28 nm CMOS process. Measurements are also presented to demonstrate the improvement in return loss and bandwidth of the transceiver.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the low frequency theory of characteristic mode 关于特征模态的低频理论
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EDAPS.2016.7874403
Q. Dai, W. Chew
{"title":"On the low frequency theory of characteristic mode","authors":"Q. Dai, W. Chew","doi":"10.1109/EDAPS.2016.7874403","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874403","url":null,"abstract":"We formulate a low frequency (LF) stabilized theory of characteristic mode (CM) to remedy LF breakdown and inaccuracy in computing dominant CMs, which are crucial for modal expansion and model order reduction in circuit applications.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121020615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of fiber weaves on 56 Gbps SerDes interface in glass epoxy packages 纤维编织对环氧玻璃封装中56gbps SerDes接口的影响
2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2016-12-01 DOI: 10.1109/EPEPS.2015.7347152
A. C. Durgun, K. Aygun
{"title":"Impact of fiber weaves on 56 Gbps SerDes interface in glass epoxy packages","authors":"A. C. Durgun, K. Aygun","doi":"10.1109/EPEPS.2015.7347152","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347152","url":null,"abstract":"Some package substrates are composed of glass fiber bundles and epoxy resin which have different electrical properties. These differences result in variations in characteristic impedance and propagation speeds, which may be detrimental at high data rates. The insertion loss (IL), within pair skew and differential to common mode conversion ratio of transmission lines may drastically increase due to the fiber weave effect. Consequently, the link budget of high speed communication channels may be significantly hindered. This paper addresses the problems due to the fiber weave effect and provides mitigation techniques at the package level, particularly for 56 Gbps Serializer/Deserializer (SerDes) interface.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128194244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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