Return loss characterization and analysis of high-speed serial interface

Abstract

This paper describes the return loss characterization and analysis of a high-speed serial interface with T-coils at the transmitter and receiver. Today's high-speed links utilize equalization to mitigate channel loss and dispersion. In addition, T-coil networks are used at inputs and outputs to improve impedance matching and to enhance the receiver and transmitter bandwidth. To guarantee the transceiver performance, a wide range of Serializer Deserializer (SerDes) compliance specifications exist for the return loss measured at or near the package interface and the Printed Circuit Board (PCB). For multi-protocol SerDes, thus, T-coil networks are often necessary to meet the most stringent return loss specification. This paper presents the analysis and characterization of a high-speed transceiver with T-coils designed in a 28 nm CMOS process. Measurements are also presented to demonstrate the improvement in return loss and bandwidth of the transceiver.