高速存储器接口的IBIS-AMI建模

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI:10.1109/EPEPS.2015.7347132

John Yan, Arash Zargaran-Yazd

{"title":"高速存储器接口的IBIS-AMI建模","authors":"John Yan, Arash Zargaran-Yazd","doi":"10.1109/EPEPS.2015.7347132","DOIUrl":null,"url":null,"abstract":"This paper presents techniques to accelerate the exploration of advanced memory links through IBIS-AMI modelling of the transmitter and receiver. The results show over 1000× CPU time speed improvement compared to full transistor level SPICE simulations while providing a fair representation of the interface performance. To demonstrate the versatility the IBIS-AMI for memory interfaces, data transmission at 2.4 Gbps and 6.4 Gbps, over the same multidrop channel with different equalization features, are presented.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"IBIS-AMI modelling of high-speed memory interfaces\",\"authors\":\"John Yan, Arash Zargaran-Yazd\",\"doi\":\"10.1109/EPEPS.2015.7347132\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents techniques to accelerate the exploration of advanced memory links through IBIS-AMI modelling of the transmitter and receiver. The results show over 1000× CPU time speed improvement compared to full transistor level SPICE simulations while providing a fair representation of the interface performance. To demonstrate the versatility the IBIS-AMI for memory interfaces, data transmission at 2.4 Gbps and 6.4 Gbps, over the same multidrop channel with different equalization features, are presented.\",\"PeriodicalId\":130864,\"journal\":{\"name\":\"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEPS.2015.7347132\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS.2015.7347132","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

本文提出了通过IBIS-AMI对发射器和接收器建模来加速探索高级存储链路的技术。结果显示，与全晶体管级SPICE模拟相比，CPU时间速度提高了1000倍以上，同时提供了一个公平的接口性能表示。为了证明IBIS-AMI在内存接口上的通用性，在2.4 Gbps和6.4 Gbps的数据传输中，采用了不同的均衡特性，在相同的多路通道上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IBIS-AMI modelling of high-speed memory interfaces

This paper presents techniques to accelerate the exploration of advanced memory links through IBIS-AMI modelling of the transmitter and receiver. The results show over 1000× CPU time speed improvement compared to full transistor level SPICE simulations while providing a fair representation of the interface performance. To demonstrate the versatility the IBIS-AMI for memory interfaces, data transmission at 2.4 Gbps and 6.4 Gbps, over the same multidrop channel with different equalization features, are presented.

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来源期刊

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)

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