GPU加速系统中高速通道设计的挑战

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI:10.1109/EPEPS.2015.7347166

Chun-Lin Liao, Terence Rodrigues, B. Mutnury

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引用次数: 1

摘要

高速服务器继续在其中部署图形处理单元(gpu)，以进行大量数据计算。高速信道上信号完整性的鲁棒性是高性能计算系统设计的一个重要因素。本文以支持多达4个GPU单元的1U / 2插座机架服务器的仿真和验证/调试过程为例，探讨了高速通道设计面临的挑战。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Challenges of high-speed channel design on GPU accelerated system

High speed servers continue to deploy graphics processing units (GPUs) in them for large volume data computation. Robustness of signal integrity on the high-speed channel is an important factor in these high performance computing (HPC) system designs. In this paper, the simulation and validation / debugging procedure of a 1U / 2 socket rack server that can support up to 4 GPU units was used as exampled to investigate the challenges on such high-speed channel design.

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2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)

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