IBIS-AMI modelling of high-speed memory interfaces

Abstract

This paper presents techniques to accelerate the exploration of advanced memory links through IBIS-AMI modelling of the transmitter and receiver. The results show over 1000× CPU time speed improvement compared to full transistor level SPICE simulations while providing a fair representation of the interface performance. To demonstrate the versatility the IBIS-AMI for memory interfaces, data transmission at 2.4 Gbps and 6.4 Gbps, over the same multidrop channel with different equalization features, are presented.