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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

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Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors 交错核激活:一种在多核多功率域处理器中减轻谐振电源噪声问题的电路/架构方法
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330673
A. Paul, Matt Amrein, Saket Gupta, Arvind Vinod, A. Arun, S. Sapatnekar, C. Kim
{"title":"Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors","authors":"A. Paul, Matt Amrein, Saket Gupta, Arvind Vinod, A. Arun, S. Sapatnekar, C. Kim","doi":"10.1109/CICC.2012.6330673","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330673","url":null,"abstract":"In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126251226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS 基于55nm CMOS的12b 200MS/s频率可扩展过零流水线ADC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330697
Soon-Kyun Shin, J. Rudell, D. Daly, C. Muñoz, D. Chang, K. Gulati, Hae-Seung Lee, M. Straayer
{"title":"A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS","authors":"Soon-Kyun Shin, J. Rudell, D. Daly, C. Muñoz, D. Chang, K. Gulati, Hae-Seung Lee, M. Straayer","doi":"10.1109/CICC.2012.6330697","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330697","url":null,"abstract":"A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFDR with a 99.6MHz input signal at 200MS/s are achieved for a FOM of 131fJ/step. The reference buffer, bias circuitry, and digital error correction circuits are all implemented on chip.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120964524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Non-invasion power monitoring with 120% harvesting energy improvement by maximum power extracting control for high sustainability power meter system 高可持续性功率计系统的非侵入式功率监测，通过最大功率提取控制可提高120%的能量收集效率
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330674
Tzu-Chi Huang, Ming-Jhe Du, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ruei-Hong Peng, Ke-Horng Chen
{"title":"Non-invasion power monitoring with 120% harvesting energy improvement by maximum power extracting control for high sustainability power meter system","authors":"Tzu-Chi Huang, Ming-Jhe Du, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ruei-Hong Peng, Ke-Horng Chen","doi":"10.1109/CICC.2012.6330674","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330674","url":null,"abstract":"Magnetic energy harvesting (MEH) circuit for system sustainability and power monitoring system with a novel dual-wire current transformer (DWCT) are proposed in this paper. MEH circuit simultaneously senses and harvests the magnetic energy. DWCT has the benefits of non-invasion measurement (NIM) and is easy to use. The designed direct AC-DC rectifier with maximum power extracting (MPE) control fits the characteristic of magnetic energy source. Thus, 120% harvesting power improvement can be achieved under the same sensing current.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116057851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology 一种123μW待机电源技术，采用28nm HKMG技术，具有容em 1.8V I/O NMOS电源开关
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330708
K. Fukuoka, Ryo Mori, A. Kato, M. Igarashi, K. Shibutani, T. Yamaki, S. Tanaka, K. Nii, S. Morita, Takao Koike, Noriaki Sakamoto
{"title":"A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology","authors":"K. Fukuoka, Ryo Mori, A. Kato, M. Igarashi, K. Shibutani, T. Yamaki, S. Tanaka, K. Nii, S. Morita, Takao Koike, Noriaki Sakamoto","doi":"10.1109/CICC.2012.6330708","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330708","url":null,"abstract":"We have developed a power-gating technique for a mobile processor in 28-nm HKMG technology. The proposed EM-tolerant 1.8V I/O NMOS power switch reduces the standby power to 1/641× and achieves 79% channel utilization without weakening EM immunity. The active leakage power of the dual CPU cores can be reduced by 45 mW in a single core operation mode with a rapid 1.4-μs wakeup time to full core operation. A mobile processor is designed and fabricated with proposed technique. Estimated standby power of the chip is 123 μW, resulting in one order of magnitude reduction compared to the conventional techniques. Measured leakage power shows a good agreement with the estimated one.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121043184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers 采用阻抗匹配传输线耦合器和Dicode部分响应通道收发器的12.5Gb/s/链路非接触多滴总线系统
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330611
Atsutake Kosuge, Wataru Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, T. Kuroda
{"title":"A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers","authors":"Atsutake Kosuge, Wataru Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, T. Kuroda","doi":"10.1109/CICC.2012.6330611","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330611","url":null,"abstract":"A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed. The transmission line has 5-convex portions to form one side of a coupler where the transmission line width is adjusted to control the characteristic impedance of the coupling section, minimizing signal reflection from each section. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI) where the test chip transmitter occupies 3,750 μm2 and the receiver occupies 750 μm2 with 90nm CMOS technology, consuming 40mA and 23mA respectively at the supply voltage of 1.2V.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123786848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs) 三维(3D)集成电路(ic)的设计和制造支持
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330588
Arifur Rahman, Hong Shi, Zhe Li, D. Ibbotson, S. Ramaswami
{"title":"Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs)","authors":"Arifur Rahman, Hong Shi, Zhe Li, D. Ibbotson, S. Ramaswami","doi":"10.1109/CICC.2012.6330588","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330588","url":null,"abstract":"This paper presents an overview of design and manufacturing readiness for silicon interposer based 3D integration. We present a field programmable gate array research and development vehicle to demonstrate the capabilities of 3D technology. The characterization results show minimal performance impact due to through silicon via (TSV) to 10Gbps transceivers and potential improvement in performance by integrating metal-insulator-metal (MIM) capacitor on silicon interposer. We also provide an overview of various process steps involved in the creation and integration of TSV on silicon interposer and methods to optimize them for performance and cost. Cost reduction can be achieved by process optimization at an integrated or holistic level, better alignment of interposer specification with application requirements, and die-package co-design.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"475 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125629860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 20 dBm Q-band SiGe Class-E power amplifier with 31% peak PAE 一个20 dBm q波段SiGe类功率放大器，峰值PAE为31%
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330563
K. Datta, J. Roderick, H. Hashemi
{"title":"A 20 dBm Q-band SiGe Class-E power amplifier with 31% peak PAE","authors":"K. Datta, J. Roderick, H. Hashemi","doi":"10.1109/CICC.2012.6330563","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330563","url":null,"abstract":"A Q-band two-stage Class-E power amplifier is designed and fabricated in a 0.13 μm SiGe HBT BiCMOS process. A mm-wave Class-E architecture considering the effect of various interconnect parasitics is adopted to achieve high power efficiency. Proper input and output networks have been designed to enable efficient switching of the HBT at large voltage swings without causing unwanted impact ionization-induced negative base current and instability. The measured performance of the fabricated chip show 20.2 dBm maximum output power, 31.5% peak power added efficiency, and 10.5 dB power gain across 4 GHz centered around 45 GHz for a supply voltage of 2.5 V. The total chip area including the pads is 0.74 mm × 1.7 mm.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132361363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Lithography and design integration — New paradigm for the technology architecture development 光刻和设计集成——技术架构发展的新范式
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330685
J. Kye, Yuansheng Ma, Lei Yuan, Yunfei Deng, H. Levinson
{"title":"Lithography and design integration — New paradigm for the technology architecture development","authors":"J. Kye, Yuansheng Ma, Lei Yuan, Yunfei Deng, H. Levinson","doi":"10.1109/CICC.2012.6330685","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330685","url":null,"abstract":"This paper proposes a new paradigm for coordination of lithography and design at advanced technology nodes. Growing complexity of technology without any lithography pitch reduction (knowing that we don't have any imminent lens NA or wavelength improvement) we need to challenge node to node scaling more than any time before. To achieve an appropriate scale factor for 20nm and beyond it is necessary to introduce double patterning. We are going to explain how we change our landscape.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126136319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 5–300MHz CMOS transceiver for multi-nuclear NMR spectroscopy 一个5-300MHz的CMOS收发器，用于多核核磁共振波谱
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330645
Jaehyup Kim, B. Hammer, R. Harjani
{"title":"A 5–300MHz CMOS transceiver for multi-nuclear NMR spectroscopy","authors":"Jaehyup Kim, B. Hammer, R. Harjani","doi":"10.1109/CICC.2012.6330645","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330645","url":null,"abstract":"This paper presents a 5-300MHz multi-nuclei NMR transceiver designed with spectroscopy for drug discovery in mind. The overall transceiver (transmitter and receiver), is implemented in 130nm CMOS, occupies an active area of 2mm2 and consumes 12mA from a 1.5V supply. The measured phase noise for the on-chip frequency synthesizer is -110dBc at 10KHz offset when the LO frequency is 212.966MHz (~1H Larmor frequency at 5T). The measured input referred noise floor for the overall receiver is 3.5nV/√Hz. The receiver NMR functionality was validated using a variety of chemical samples, including adenosine triphosphaste(ATP), benzene(C6H6) and ethanol(CH3CH2OH) in a 5T magnet. Full transceiver NMR functionality, including that of of the internal power amplifier, was validated with the help of a 0.3mL H2O sample.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129953456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator 用于硅电光环调制器的低功耗，10gbps 1.5 vpp差分CMOS驱动器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330643
M. Rakowski, J. Ryckaert, M. Pantouvaki, Hui Yu, W. Bogaerts, K. Meyer, M. Steyaert, P. Absil, J. Campenhout
{"title":"Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator","authors":"M. Rakowski, J. Ryckaert, M. Pantouvaki, Hui Yu, W. Bogaerts, K. Meyer, M. Steyaert, P. Absil, J. Campenhout","doi":"10.1109/CICC.2012.6330643","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330643","url":null,"abstract":"We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5Vpp from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1Vpp and 1.5Vpp respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129770439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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