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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

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Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules 用于x86-64 AMD微处理器模块的软边触发器的设计与实现
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330707
S. Dillen, D. Priore, Aaron Horiuchi, S. Naffziger
{"title":"Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules","authors":"S. Dillen, D. Priore, Aaron Horiuchi, S. Naffziger","doi":"10.1109/CICC.2012.6330707","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330707","url":null,"abstract":"This paper presents the design and implementation of a family of high-performance soft-edge flip-flops (SEF) used in AMD products with core modules code-named “Bulldozer.” We highlight the benefits of the SEF and introduce a new method for comparing flip-flop designs in the presence of clock jitter. We describe an area-efficient level-sensitive scan design (LSSD) implementation in conjunction with supporting clock-gating circuitry for stand-by power reduction. We compare different SEF topologies along with flip-flops from previous designs.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129443052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Statistical aging under dynamic voltage scaling: A logarithmic model approach 动态电压标度下的统计老化:一种对数模型方法
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330572
J. Velamala, K. Sutaria, Hirofumi Shimizu, H. Awano, Takashi Sato, Yu Cao
{"title":"Statistical aging under dynamic voltage scaling: A logarithmic model approach","authors":"J. Velamala, K. Sutaria, Hirofumi Shimizu, H. Awano, Takashi Sato, Yu Cao","doi":"10.1109/CICC.2012.6330572","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330572","url":null,"abstract":"Aging mechanisms, such as Negative Bias Temperature Instability (NBTI), limit the lifetime of CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction in real circuit operation. To overcome these barriers, this work (1) proposes a logarithmic model (log(t)) that is derived from the trapping/de-trapping assumptions; (2) practically explains the aging statistics and the non-monotonic behavior under dynamic voltage scaling (DVS); and (3) comprehensively validates the new model with 65nm silicon data. Compared to previous models, the new result captures the essential role of the recovery phase under DVS, reducing unnecessary guard-banding in reliability protection.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129537350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control 7b1gs /s 7.2mW非二进制2b/周期SAR ADC，具有寄存器到dac的直接控制
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330609
Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Hojin Park, S. Ryu
{"title":"A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control","authors":"Hyeok-Ki Hong, Wan Kim, Sun-Jae Park, Michael Choi, Hojin Park, S. Ryu","doi":"10.1109/CICC.2012.6330609","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330609","url":null,"abstract":"A 45nm CMOS 7b nonbinary 2b/cycle SAR ADC that operates up to 1GS/s with a 1.25V supply is presented. Use of a nonbinary decision scheme for decision error correction in a 2b/cycle structure not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuation and signal-dependent comparator offset variation. Proposed dynamic registers and a register-to-DAC direct control scheme enhance the conversion speed by minimizing logic delay in the decision loop. At a sampling rate of 1 GS/s, the chip achieves a peak SNDR of 41.6dB and maintains ENOB higher than 6b up to 1.3GHz signal frequency. The FoM is 80fJ/ conversion-step at 1GS/s with a power consumption of 7.2mW.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130954681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS 一个基于45nm SOI CMOS的3.2GS/s 4.55b ENOB两步分位ADC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330610
J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, Michael P. Beakes, J. Tierno, D. Friedman
{"title":"A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS","authors":"J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, Michael P. Beakes, J. Tierno, D. Friedman","doi":"10.1109/CICC.2012.6330610","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330610","url":null,"abstract":"A 3.2GS/s two-step subranging ADC is implemented in a 45nm SOI-CMOS technology. The measured ENOB is 4.55b at 1.6GHz. The IIP3 is -1.1dBm. The power consumption is 22mW from a 1.05V voltage supply for a FOM of 290fJ/ conversion-step. The chip occupies an active area of 0.07mm2.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116335075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fully depleted devices for designers: FDSOI and FinFETs 专为设计人员设计的全耗尽器件:FDSOI和finfet
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330653
T. Hook
{"title":"Fully depleted devices for designers: FDSOI and FinFETs","authors":"T. Hook","doi":"10.1109/CICC.2012.6330653","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330653","url":null,"abstract":"Technologies featuring fully depleted transistors are entering the mainstream for designs at the 28nm, 20nm, and 14nm nodes. Although these devices have been the playground of device engineers for more than a decade it is for the most part only recently that they have been introduced to circuit designers and logic chip integrators. The physical structure and many of the features - or lack thereof - of the transistors vis-à-vis conventional planar devices are different, opening some new doors and perhaps closing some old ones. In this paper we discuss both planar (variously called ETSOI/UTBB/FDSOI1) and three-dimensional (variously called FinFET or trigate or doublegate) fully depleted devices, comparing and contrasting them with one another and with classical devices, and in both bulk and SOI manifestations.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"162 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129174586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction 一个0.015mm2 63fJ/转换步10位220MS/s SAR ADC, 1.5b/步冗余和数字亚稳校正
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330696
R. Vitek, E. Gordon, S. Maerkovich, A. Beidas
{"title":"A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction","authors":"R. Vitek, E. Gordon, S. Maerkovich, A. Beidas","doi":"10.1109/CICC.2012.6330696","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330696","url":null,"abstract":"A low power and very low area 10-bit 220MS/s SAR ADC is presented. The ADC employs a redundancy scheme that relaxes the DAC settling requirement and enables high sample rates, as well as a digital metastability identification and correction algorithm that exploits the redundancy as an error-correction code. The proposed ADC was implemented in CMOS 65nm, and takes up only 0.015mm2. At 220MS/s it consumes 4.3mW and achieves 51.7dB SNDR for a full scale sinusoidal input. For OFDM-like signals (wide-band 13dB Peak-to-RMS) the equivalent ENOB is 9.1 bit at 220MS/s. The figure-of-merit (FOM) is 63fJ/(conversion-step) at 220MS/s and 43fJ/conv-step at 160Ms/s.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127017445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Extremely thin SOI for system-on-chip applications 用于片上系统应用的极薄SOI
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330618
Ali Khaki-Firooz, K. Cheng, Qing Liu, T. Nagumo, N. Loubet, A. Reznicek, J. Kuss, J. Gimbert, R. Sreenivasan, M. Vinet, L. Grenouillet, Y. L. Tiec, R. Wacquez, Z. Ren, J. Cai, D. Shahrjerdi, P. Kulkarni, S. Ponoth, S. Luning, B. Doris
{"title":"Extremely thin SOI for system-on-chip applications","authors":"Ali Khaki-Firooz, K. Cheng, Qing Liu, T. Nagumo, N. Loubet, A. Reznicek, J. Kuss, J. Gimbert, R. Sreenivasan, M. Vinet, L. Grenouillet, Y. L. Tiec, R. Wacquez, Z. Ren, J. Cai, D. Shahrjerdi, P. Kulkarni, S. Ponoth, S. Luning, B. Doris","doi":"10.1109/CICC.2012.6330618","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330618","url":null,"abstract":"We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of VT tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117006718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example SystemVerilog中模拟/混合信号行为的真正事件驱动仿真:一个决策反馈均衡(DFE)接收器示例
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330558
Jieun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim
{"title":"True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example","authors":"Jieun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim","doi":"10.1109/CICC.2012.6330558","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330558","url":null,"abstract":"This paper presents a true event-driven simulation methodology for analog/mixed signal systems. To avoid generation of new output events without an input event, analog waveforms are expressed as a set of parameter values for an analytical basis function, c·tm-1e-at·u(t). Also, the s-domain analysis enables an algebraic computation of the output event without involving timestep integration. The proposed methodology implemented in SystemVerilog is demonstrated with a decision-feedback equalizer (DFE) example. The experimental results show that both the speed and accuracy of the simulation depend very weakly on the time step resolution, supporting that a true event-driven simulation is realized.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132544622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
0.61W/mm2 resonant inductively coupled power transfer for 3D-ICs 3d - ic的0.61W/mm2谐振电感耦合功率传输
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330590
Sangwoo Han, D. Wentzloff
{"title":"0.61W/mm2 resonant inductively coupled power transfer for 3D-ICs","authors":"Sangwoo Han, D. Wentzloff","doi":"10.1109/CICC.2012.6330590","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330590","url":null,"abstract":"A high power density wireless inductive power link targeting 3D-ICs and wireless testing is implemented in 65nm CMOS. Its operating frequency is 3.5GHz, the optimal frequency from the trade-off between delivered power and power loss. The link exploits high-Q inductors and resonant inductive coupling to boost the received voltage and maximize the delivered power. A power density of 0.61W/mm2 is achieved with 0.12×0.12mm2 coils and a 50μm separation.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132728585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Advanced IC technologies I 先进集成电路技术1
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330656
A. Loke, D. Sunderland
{"title":"Advanced IC technologies I","authors":"A. Loke, D. Sunderland","doi":"10.1109/CICC.2012.6330656","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330656","url":null,"abstract":"This all-Invited session covers advanced technologies, including the first production tri-gate devices, ultra-thin SOI, reliability challenges for scaled CMOS, and SiC devices for power management.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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