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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

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High-speed wireline transceivers and clocking 高速有线收发器和时钟
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330575
G. D. Besten, S. Kaeriyama
{"title":"High-speed wireline transceivers and clocking","authors":"G. D. Besten, S. Kaeriyama","doi":"10.1109/CICC.2012.6330575","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330575","url":null,"abstract":"High-speed wireline communication links are ubiquitous in electronic systems today. Continuous research is pushing speed, power efficiency, flexibility, and ease-of-use of interfaces. This session includes some to latest advances in the wireline domain.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133184876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A wideband ultra-low-current on-chip ammeter 一种宽带超低电流片上安培计
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330668
Junjie Lu, J. Holleman
{"title":"A wideband ultra-low-current on-chip ammeter","authors":"Junjie Lu, J. Holleman","doi":"10.1109/CICC.2012.6330668","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330668","url":null,"abstract":"A high-bandwidth ultra-low-current measurement circuit is presented in this paper. The circuit is capable of measuring an on-chip 75 fA current at a bandwidth up to 1 kHz with a noise floor of 0.235 fArms/√Hz. A low leakage reset scheme is utilized to improve the precision. Nested auto-zeroing combined with modified correlated double sampling is employed to mitigate the error due to various circuit imperfections. Noise analysis is carried out and “capacitive noise matching” is proposed to minimize the noise floor. The circuit is also capable of digitizing the measured current and streaming the data through a serial interface. The measurement circuit occupies 0.065 mm2 of active silicon area in a 90 nm CMOS process and consumes 147 μW from 2.5 V and 1V supplies.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122424145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Reliability challenges for the continued scaling of IC technologies 集成电路技术持续扩展带来的可靠性挑战
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330658
A. Oates
{"title":"Reliability challenges for the continued scaling of IC technologies","authors":"A. Oates","doi":"10.1109/CICC.2012.6330658","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330658","url":null,"abstract":"The rapid evolution of Si process technologies presents significant challenges to the understanding of the physics of failure of circuits and the characterization of their reliability. Introduction of new materials at the 28 nm node and below, as well as new FinFET transistor structures, complicates the task of reliability assurance. Here we review the major reliability challenges for transistors, interconnect and circuits that can be foreseen with these scaling trends.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127692317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Problem of timing mismatch in interleaved ADCs 交错adc的时序失配问题
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330655
B. Razavi
{"title":"Problem of timing mismatch in interleaved ADCs","authors":"B. Razavi","doi":"10.1109/CICC.2012.6330655","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330655","url":null,"abstract":"Time interleaving can relax the speed-power trade-off of analog-to-digital converters but at the cost of sensitivity to interchannel mismatches. This paper addresses the problem of timing mismatch, its detection, and its correction. A new frequency-domain analysis gives insight into the impact of the mismatch on random input signals and quantifies the resulting noise. A number of timing error calibration techniques are reviewed and a new approach is proposed.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS 双稳态和基于延迟的物理不可克隆函数在65nm CMOS测量中的比较
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330625
M. Bhargava, Cagla Cakir, K. Mai
{"title":"Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS","authors":"M. Bhargava, Cagla Cakir, K. Mai","doi":"10.1109/CICC.2012.6330625","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330625","url":null,"abstract":"Physical Unclonable Functions (PUFs) are security primitives used in a number of security applications like authentication, identification, and secure key generation. PUF implementations are evaluated on their security characteristics (uniqueness, randomness, and reliability), as well as conventional VLSI design metrics (area, power, and performance). We compare bi-stable based PUFs (SRAM and sense amplifiers) and delay based PUFs (arbiter and ring oscillator) using measurements from a testchip in 65nm bulk CMOS. Security metrics are measured on multiple dies and reliability measurements are based on multiple evaluations of PUF circuits across operating voltage (1.0V to 1.4V) and temperature (-20°C to 85°C).","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129297041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
High-speed data converters 高速数据转换器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330606
E. Naviasky, Mohammad Ranjbar
{"title":"High-speed data converters","authors":"E. Naviasky, Mohammad Ranjbar","doi":"10.1109/CICC.2012.6330606","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330606","url":null,"abstract":"High-speed data converters have become an integral part of wide-band wireless, wireline and networking applications with ever increasing data rates. In such systems reducing the power consumption of the A/D converter while increasing its sampling rate and linearity has remained a challenge. This fact has motivated many research groups to investigate potential solutions, which some of these efforts are highlighted in the following papers.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117115451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz 4.8mW无电感的CMOS分频器，带宽超过60%，最高可达70GHz
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330595
A. Ghilioni, U. Decanis, A. Mazzanti, F. Svelto
{"title":"A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz","authors":"A. Ghilioni, U. Decanis, A. Mazzanti, F. Svelto","doi":"10.1109/CICC.2012.6330595","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330595","url":null,"abstract":"Frequency synthesizers at mm-waves would benefit from wide-band low-power dividers with large division factors. This work proposes a divider-by-4 based on clocked differential amplifiers working as dynamic CML latches. The clock modulates both the tail current and the load resistance of the differential pair, allowing a wide locking range. Prototypes, realized in 32nm CMOS, operate between 14GHz and 70GHz demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8mW of maximum power consumption and 55×18μm2 occupied area.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117215860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS 40nm低功耗CMOS中27 Gb/s、0.41 mw /Gb/s单抽头预测决策反馈均衡器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330684
K. Kaviani, Masum Hossain, M. H. Nazari, F. Heaton, Jihong Ren, J. Zerbe
{"title":"A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS","authors":"K. Kaviani, Masum Hossain, M. H. Nazari, F. Heaton, Jihong Ren, J. Zerbe","doi":"10.1109/CICC.2012.6330684","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330684","url":null,"abstract":"A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128093853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Energy-efficient architecture and enabling technology for advanced SOCs 先进soc的节能架构和使能技术
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330635
Arifur Rahman, L. Clark
{"title":"Energy-efficient architecture and enabling technology for advanced SOCs","authors":"Arifur Rahman, L. Clark","doi":"10.1109/CICC.2012.6330635","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330635","url":null,"abstract":"This session highlights energy-efficient architectures, implementations of application-specific SoC in advanced process technologies, and silicon photonics building blocks for chip-scale optical interconnects.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Online Reinforcement Learning NoC for portable HD object recognition processor 便携式高清物体识别处理器的在线强化学习NoC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330637
Junyoung Park, Injoon Hong, Gyeonghoon Kim, Jinwook Oh, Seungjin Lee, H. Yoo
{"title":"Online Reinforcement Learning NoC for portable HD object recognition processor","authors":"Junyoung Park, Injoon Hong, Gyeonghoon Kim, Jinwook Oh, Seungjin Lee, H. Yoo","doi":"10.1109/CICC.2012.6330637","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330637","url":null,"abstract":"Heterogeneous multi-core object recognition processor with Reinforcement Learning (RL) NoC is proposed for efficient portable HD object recognition. RL NoC automatically learns management policies in the network of heterogeneous system without an explicit modeling. By adopting RL NoC, the throughput performances of feature detection and description are increased by 20.4% and 11.5%, respectively. As a result, the overall execution time of the object recognition is reduced by 38%. The implemented chip achieves 121mW power consumption with 1.24 TOPS/W power efficiency.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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