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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

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Field programmable SONOS ESD protection design 现场可编程SONOS ESD保护设计
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330711
Jian Liu, Zitao Shi, Xin Wang, H Zhao, L. Wang, Chen Zhang, Z. Dong, L. Lin, Albert Z. H. Wang, Yuhua Cheng, Bin Zhao
{"title":"Field programmable SONOS ESD protection design","authors":"Jian Liu, Zitao Shi, Xin Wang, H Zhao, L. Wang, Chen Zhang, Z. Dong, L. Lin, Albert Z. H. Wang, Yuhua Cheng, Bin Zhao","doi":"10.1109/CICC.2012.6330711","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330711","url":null,"abstract":"This paper reports the first SONOS-based field-programmable ESD protection concept and structure. Prototype in 130nm CMOS demonstrates wide ESD triggering tuning range of ~2V and ultra low leakage of 1.2pA. It enables post-Si on-chip/in-system ESD design programmability for complex ICs.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"394 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133546047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Phase Change Memory: Scaling and applications 相变存储器:扩展和应用
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330621
R. Jeyasingh, Jiale Liang, Marissa Caldwell, D. Kuzum, H. Wong
{"title":"Phase Change Memory: Scaling and applications","authors":"R. Jeyasingh, Jiale Liang, Marissa Caldwell, D. Kuzum, H. Wong","doi":"10.1109/CICC.2012.6330621","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330621","url":null,"abstract":"Phase Change Memory (PCM) technology is a promising candidate for the future non-volatile memory applications. Scaling of PCM into the sub-10 nm regime has been demonstrated using novel applications of nanofabrication techniques. PCM devices using solution-processed GeTe nanoparticles of diameter range 1.8-3.4nm has been demonstrated. Highly scaled (<;2nm) PCM cross-point device using carbon nanotube as the electrode is fabricated proving the scalability of PCM to ultra small dimensions. The use of PCM as a nanoelectronic synapse for neuromorphic computation is also demonstrated as an illustration of PCM application beyond digital memory.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129650346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Design of a monolithic CMOS image sensor integrated focal plane wire-grid polarizer filter mosaic 集成焦平面线栅偏振滤波器马赛克的单片CMOS图像传感器设计
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330605
Xiaotie Wu, Milin Zhang, N. Engheta, J. Spiegel
{"title":"Design of a monolithic CMOS image sensor integrated focal plane wire-grid polarizer filter mosaic","authors":"Xiaotie Wu, Milin Zhang, N. Engheta, J. Spiegel","doi":"10.1109/CICC.2012.6330605","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330605","url":null,"abstract":"Polarization is one of the important characteristics of visible light that can not be detected by human visual system or traditional image sensors. In this paper, we report on an image sensor integrated focal plane 2 × 2 wire-grid polarizer filter mosaic targeted at visible spectrum fabricated in 65nm standard CMOS processing line, which enables the reconstruction of the polarization response characteristic for each pixel. Finite-Difference Time-Domain method has been used for the first time to optimize the extinction ratio in visible spectrum of the multilayer focal plane wire-grid polarizer. Experimental results show that an extinction ratio around 10 is achieved with a standard error of around 0.25% between the experimental results and the fitting sinusoidal polarization response curve. A phase error at the level of less than 2% to the measurement phase resolution is achieved. These results are the best reported for a monolithic wire-grid polarization image sensor design for visible spectrum.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132213327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 0.6V 2.2mW 58-to-73GHz divide-by-4 injection-locked frequency divider 一个0.6V 2.2mW 58至73ghz分频器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330594
Liang Wu, H. Luong
{"title":"A 0.6V 2.2mW 58-to-73GHz divide-by-4 injection-locked frequency divider","authors":"Liang Wu, H. Luong","doi":"10.1109/CICC.2012.6330594","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330594","url":null,"abstract":"A simple but effective locking range enhancement technique is proposed for LC-type divide-by-4 injection-locked frequency dividers (ILFDs) at millimeter-wave (mm-Wave) frequencies. By employing a 4th-order LC tank with the two frequency peaks properly designed at ω0 and 3ω0, the 3rd-order harmonic gets boosted that significantly enhances the injection efficiency and thus the locking range of divide-by-4 ILFDs. Implemented in 65-nm CMOS, the prototype measures a locking range of 21.9% from 58.53 to 72.92 GHz while consuming 2.2mW from a 0.6V-supply, which corresponds to an FoM of 6.54.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132247813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Electronic design automation (EDA) solutions for ESD-robust design and verification 电子设计自动化(EDA)解决方案的esd稳健设计和验证
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330690
M. Khazhinsky, S. Cao, H. Gossner, G. Boselli, M. Etherton
{"title":"Electronic design automation (EDA) solutions for ESD-robust design and verification","authors":"M. Khazhinsky, S. Cao, H. Gossner, G. Boselli, M. Etherton","doi":"10.1109/CICC.2012.6330690","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330690","url":null,"abstract":"The paper describes the essential requirements of the Electrostatic Discharge (ESD) EDA verification flow to be aligned within the IC design community. The proposed flow offers a systematic approach to check ESD robustness across all IC blocks during the product definition, chip architecture, main module and full IC design phases, and during the final IC verification. This flow is substantiated by case studies of key ESD checks at different IC design stages, demonstrating the necessity of replacing manual checks with EDA tool enabled verification.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132456826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-phase-noise wide-tuning-range quadrature oscillator in 65nm CMOS 一种65nm CMOS低相位噪声宽调谐范围正交振荡器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330682
Guansheng Li, E. Afshari
{"title":"A low-phase-noise wide-tuning-range quadrature oscillator in 65nm CMOS","authors":"Guansheng Li, E. Afshari","doi":"10.1109/CICC.2012.6330682","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330682","url":null,"abstract":"In this paper, we present a low-phase-noise wide-tuning-range quadrature oscillator using an LC-ring resonator. It achieves low phase noise by employing passive coupling between multiple stages and at the same time it covers a wide tuning range by switching between two resonant modes. Furthermore, the problem of oscillation frequency uncertainty which is a common issue in oscillators with multiple oscillation modes is addressed by the novel mode switching method. The proposed design is verified by a four-stage LC-ring prototype in a 65nm CMOS process, which covers 2.78GHz-5.00GHz with phase noise FoM of 186dB at 3.66GHz and >;180dB across the entire tuning range. This demonstrates the best performance among wide-tuning-range quadrature VCO's at this frequency range.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"17 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114115648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS 具有65纳米CMOS可重构开关电容转换器的EChO电源管理单元
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330629
M. Alioto, Elio Consoli, J. Rabaey
{"title":"EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS","authors":"M. Alioto, Elio Consoli, J. Rabaey","doi":"10.1109/CICC.2012.6330629","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330629","url":null,"abstract":"In this paper, a novel reconfigurable power management unit (PMU) is introduced. Its reconfigurable switched capacitor array permits for the first time to reduce the energy cost associated with sleep-to-active and active-to sleep transitions by 64%. This energy reduction comes at small area overhead (lower than 1%) and no penalty in active mode. Measurements on a 65-nm testchip comprising of PMU with integrated logic and memory show that energy savings enabled by our technique are in the order of 30% in practical cases.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114317961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Intel Ivy Bridge unveiled — The first commercial tri-gate, high-k, metal-gate CPU 英特尔长春藤桥揭幕——第一款商用三门、高k、金属门CPU
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330644
D. James
{"title":"Intel Ivy Bridge unveiled — The first commercial tri-gate, high-k, metal-gate CPU","authors":"D. James","doi":"10.1109/CICC.2012.6330644","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330644","url":null,"abstract":"The year 2007 saw the introduction of the first high-k/metal gate (HKMG) devices into the marketplace. This marked the return of metal-gate technology on silicon for the first time since polysilicon gates became ubiquitous in the early 1970s. Intel was the first to use high-k/metal gate in its 45-nm product. Other leading-edge manufacturers have now launched HKMG products in both gate-first and gate-last forms, and now the first 22-nm FinFET products have come onto the market - the Intel Ivy Bridge CPU. Chipworks, as a supplier of competitive intelligence to the semiconductor and electronics industries, monitors the evolution of chip processes as they come into commercial production. Chipworks has obtained samples of this leading-edge part and performed structural analyses to examine the features and manufacturing processes of the device. This paper discusses some of the different features we have seen within the chip, and illustrates the structure of the tri-gate transistors.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122425231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
A mixed-mode FPAA SoC for analog-enhanced signal processing 一种用于模拟增强信号处理的混合模式FPAA SoC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330679
Craig Schlottmann, Stephen Nease, Samuel A. Shapero, P. Hasler
{"title":"A mixed-mode FPAA SoC for analog-enhanced signal processing","authors":"Craig Schlottmann, Stephen Nease, Samuel A. Shapero, P. Hasler","doi":"10.1109/CICC.2012.6330679","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330679","url":null,"abstract":"We present the RASP 2.9v, an FPAA for mixed-signal computation with an emphasis on enhanced digital support. This 25mm2, 350nm CMOS chip includes on-chip compilable DACs, dynamic reconfigurability and digital storage, and 76,000 programmable elements. We demonstrate an analog image-transform processor, an arbitrary waveform generator, and a mixed-mode FIR filter.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116323336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design solutions for 3D integration and signal integrity 设计3D集成和信号完整性的解决方案
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330687
Yu Cao, S. Mudanai
{"title":"Design solutions for 3D integration and signal integrity","authors":"Yu Cao, S. Mudanai","doi":"10.1109/CICC.2012.6330687","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330687","url":null,"abstract":"Design robustness is increasingly challenging in large-scale system integration. This session presents solutions to 3D integration, ESD, and on-chip interconnect.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115687436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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