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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

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Amorphous silicon 5 bit flash analog to digital converter 非晶硅5位闪存模拟数字转换器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330647
A. Dey, D. Allee
{"title":"Amorphous silicon 5 bit flash analog to digital converter","authors":"A. Dey, D. Allee","doi":"10.1109/CICC.2012.6330647","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330647","url":null,"abstract":"A 5-bit fully flash A/D converter (ADC) is built using only n-channel amorphous silicon hydride (a-Si:H) thin film transistors (TFT), metal resistors and capacitors. The circuit is built on silicon using a low temperature process, compatible with flexible plastic substrates. The circuit consumes a power of 13.6 mW running at a speed of 2 k samples/sec. The measurements show reasonably good characteristics, achieving a DNL of less than ±1 LSB and INL of less than ±1.8 LSB without calibration.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 695 pW standby power optical wake-up receiver for wireless sensor nodes 一种用于无线传感器节点的695 pW备用功率光唤醒接收器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330603
Gyouho Kim, Yoonmyung Lee, S. Bang, Inhee Lee, Yejoong Kim, D. Sylvester, D. Blaauw
{"title":"A 695 pW standby power optical wake-up receiver for wireless sensor nodes","authors":"Gyouho Kim, Yoonmyung Lee, S. Bang, Inhee Lee, Yejoong Kim, D. Sylvester, D. Blaauw","doi":"10.1109/CICC.2012.6330603","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330603","url":null,"abstract":"We propose an ultra-low power optical wake-up receiver with a novel front-end circuit and communication scheme suitable for miniature wireless sensor node applications. Named “FLOW” for Free-space Low-Power Optical Wake-up, the receiver consumes 695pW in standby mode, which is ~6,000× lower than previously reported RF and ultrasound wake-up radios. In active mode, it consumes 140pJ/bit at 91bps. A pulse width modulated communication encoding scheme is used, and chip-ID masking enables selective batch-programming and synchronization of multiple sensor nodes.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116433053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
CMOS handset power amplifiers: Directions for the future CMOS手机功率放大器:未来的方向
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330561
P. Asbeck, L. Larson, D. Kimball, J. Buckwalter
{"title":"CMOS handset power amplifiers: Directions for the future","authors":"P. Asbeck, L. Larson, D. Kimball, J. Buckwalter","doi":"10.1109/CICC.2012.6330561","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330561","url":null,"abstract":"While the present market for power amplifiers in wireless handsets is largely met by GaAs HBTs, CMOS technology can provide major advantages including high integration levels, scalability, and digital control. This paper reviews possible directions for future CMOS PA development including FET stacking, envelope tracking, digital predistortion, and new architectures based on digital control, that promise to add to the advantages of CMOS in LTE applications.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122905988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Designing reliable analog circuits in an unreliable world 在一个不可靠的世界中设计可靠的模拟电路
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330571
G. Gielen, Elie Maricau, P. D. Wit
{"title":"Designing reliable analog circuits in an unreliable world","authors":"G. Gielen, Elie Maricau, P. D. Wit","doi":"10.1109/CICC.2012.6330571","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330571","url":null,"abstract":"Reliability is one of the major concerns in designing integrated circuits in deep nanometer CMOS technologies. Problems related to transistor aging like BTI or soft breakdown cause time-dependent circuit performance degradation. Variability only makes these things more severe. This creates a need for innovative design techniques and tools that help designers coping with these reliability and variability problems. This invited overview paper gives a brief description of device aging models. It also presents tools for the efficient analysis and identification of reliability problems in analog circuits. Finally, it proposes solutions for the design of resilient, self-healing circuits.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
FEC-based 4 Gb/s backplane transceiver in 90nm CMOS 90nm CMOS中基于fec的4gb /s背板收发器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330665
Adam C. Faust, R. Narasimha, K. Bhatia, Ankit Srivastava, C. Kong, Hyeon-Min Bae, E. Rosenbaum, Naresh R Shanbhag
{"title":"FEC-based 4 Gb/s backplane transceiver in 90nm CMOS","authors":"Adam C. Faust, R. Narasimha, K. Bhatia, Ankit Srivastava, C. Kong, Hyeon-Min Bae, E. Rosenbaum, Naresh R Shanbhag","doi":"10.1109/CICC.2012.6330665","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330665","url":null,"abstract":"This paper presents the first reported design of a forward error correction (FEC)-based high-speed serial link. A 4 Gb/s line rate transceiver in 90nm CMOS is designed with short block length BCH codes. FEC is shown to be effective for high code rates, high information rates and low SNR channels. Measurement results of the transceiver over a 18.2 dB Nyquist loss channel show a 45× reduction in minimum BER, and an increase in jitter tolerance at low transmit swings. For a BER <; 1012, the addition of FEC reduces the required transmit signal swing, from approximately 0.75 Vppd to less than 0.5 Vppd.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC 连续时间ΔΣ调制器，动态范围87 dB, 2MHz信号带宽，使用开关电容归零DAC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330692
T. Nandi, Karthikeya Boominathan, S. Pavan
{"title":"A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC","authors":"T. Nandi, Karthikeya Boominathan, S. Pavan","doi":"10.1109/CICC.2012.6330692","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330692","url":null,"abstract":"We introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low distortion of a Return-to-Zero DAC. A single-bit continuous-time ΔΣ modulator that uses the SCRZ technique and opamp-assistance to improve DAC linearity and reduce jitter sensitivity achieves 87.1/84.5/82.3 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at a sampling rate of 256 MHz in a 0.18 μm CMOS process, the CTDSM dissipates 16.5 mW from a 1.8 V supply.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127579852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS 一个0.1 ~ 4GHz的接收器和0.1 ~ 6GHz的发射器，在65nm CMOS中具有可重构的10 ~ 100MHz信号带宽
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330680
Xinwang Zhang, Yun Yin, Mengdi Cao, Zhigang Sun, Ling Fu, Zhaokang Xia, Hongxing Feng, Xing Zhang, B. Chi, Ming Xu, Zhihua Wang
{"title":"A 0.1∼4GHz receiver and 0.1∼6GHz transmitter with reconfigurable 10∼100MHz signal bandwidth in 65nm CMOS","authors":"Xinwang Zhang, Yun Yin, Mengdi Cao, Zhigang Sun, Ling Fu, Zhaokang Xia, Hongxing Feng, Xing Zhang, B. Chi, Ming Xu, Zhihua Wang","doi":"10.1109/CICC.2012.6330680","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330680","url":null,"abstract":"A 8.12mm2 0.1-4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS is presented. Rx features two single-ended LNAs in parallel, passive current down-conversion with 25% duty-cycle LOs, 5th/7th-order reconfigurable baseband filtering and IIP2/frequency tuning/IQ calibration. It achieves NF of 3~8dB over 0.1-4GHz and 21mA current consumption for 2.3GHz LTE with 20MHz signal bandwidth. Fully-integrated Tx features reconfigurable PPAs with transformer differential-single-ended conversion output, a low-noise sub-path and high dynamic range main-path as well as LO leakage and image rejection calibration. It achieves 1.7% EVM for 1.8GHz WCDMA with 1.5dBm output power, -31/-51 ACLR1/ACLR2 for 2.3GHz LTE with 20MHz bandwidth at 3dBm output power, <;-42dBc LO feedthrough and >;51dBc image rejection.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128472254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibration 7b 1.4GS/s ADC，带偏移漂移抑制技术，可进行一次性校准
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330608
Yuji Nakajima, Norihito Kato, Akemi Sakaguchi, Toshio Ohkido, Kenji Shimomaki, H. Masuda, Chikahiro Shiroma, M. Yotsuyanagi, T. Miki
{"title":"A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibration","authors":"Yuji Nakajima, Norihito Kato, Akemi Sakaguchi, Toshio Ohkido, Kenji Shimomaki, H. Masuda, Chikahiro Shiroma, M. Yotsuyanagi, T. Miki","doi":"10.1109/CICC.2012.6330608","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330608","url":null,"abstract":"A 7b 1.4 GS/s flash ADC is developed in 45 nm CMOS. This is the first paper of an ADC with offset drift suppression techniques for dynamic comparator and preamplifier. These techniques make the ADC robust against environmental variation. As a result, once the ADC is calibrated at power up, no more calibration is necessary even under VDD or temperature variations. The ADC occupies a small area of 0.085 mm2 and dissipates 33.24 mW at 1.4 GS/s from a 1.15V supply.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127585315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization 28nm HKMG GHz数字传感器，用于检测峰值功率优化测试中的动态电压降
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330710
M. Igarashi, K. Takeuchi, Y. Takazawa, Y. Igarashi, Hiroaki Matsushita
{"title":"28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization","authors":"M. Igarashi, K. Takeuchi, Y. Takazawa, Y. Igarashi, Hiroaki Matsushita","doi":"10.1109/CICC.2012.6330710","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330710","url":null,"abstract":"We propose a dynamic voltage-drop sensor, which is fully digital so that it is easy to design into products and use for testing. The 2.4K-gate GHz sensor exploits the difference in the voltage sensitivity between two paths composed of different types of standard cells. We have fabricated a test chip in a 28-nm HKMG process and confirmed its feasibility. This sensor can be used to evaluate optimal activity rates and peak power in scan testing.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Data converter techniques 数据转换器技术
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330691
Ron Kapusta, Yuji Nakajima
{"title":"Data converter techniques","authors":"Ron Kapusta, Yuji Nakajima","doi":"10.1109/CICC.2012.6330691","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330691","url":null,"abstract":"The papers in this session highlight innovative architectures and circuit techniques to improve performance and reduce power consumption of analog-to-digital converters (ADC's).","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124106202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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