A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC

T. Nandi, Karthikeya Boominathan, S. Pavan
{"title":"A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC","authors":"T. Nandi, Karthikeya Boominathan, S. Pavan","doi":"10.1109/CICC.2012.6330692","DOIUrl":null,"url":null,"abstract":"We introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low distortion of a Return-to-Zero DAC. A single-bit continuous-time ΔΣ modulator that uses the SCRZ technique and opamp-assistance to improve DAC linearity and reduce jitter sensitivity achieves 87.1/84.5/82.3 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at a sampling rate of 256 MHz in a 0.18 μm CMOS process, the CTDSM dissipates 16.5 mW from a 1.8 V supply.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2012.6330692","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

We introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low distortion of a Return-to-Zero DAC. A single-bit continuous-time ΔΣ modulator that uses the SCRZ technique and opamp-assistance to improve DAC linearity and reduce jitter sensitivity achieves 87.1/84.5/82.3 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at a sampling rate of 256 MHz in a 0.18 μm CMOS process, the CTDSM dissipates 16.5 mW from a 1.8 V supply.
连续时间ΔΣ调制器,动态范围87 dB, 2MHz信号带宽,使用开关电容归零DAC
我们介绍了开关电容归零(SCRZ) DAC,它结合了开关电容DAC的低时钟抖动灵敏度和归零DAC的低失真。单比特连续时间ΔΣ调制器使用SCRZ技术和运放大器辅助来提高DAC线性度并降低抖动灵敏度,在2 MHz带宽下实现87.1/84.5/82.3 dB DR/SNR/SNDR。CTDSM采用0.18 μm CMOS工艺,采样率为256 MHz,在1.8 V电源下功耗为16.5 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信