Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integration 10.35 mW/GFlop叠加SAR DSP单元，采用细粒度分区3D集成

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330589

T. Thorolfsson, S. Lipa, P. Franzon

引用次数: 13

A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 μm CMOS technology 基于0.18 μm CMOS技术的100mhz两相四段DC-DC轻负载效率增强变换器

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330631

Han Peng, David I. Anderson, M. Hella

引用次数: 8

An integrated MESFET voltage follower LDO for high power and PSR RF and analog applications 集成MESFET电压跟随器LDO，用于高功率和PSR RF和模拟应用

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330634

W. Lepkowski, S. Wilk, M. R. Ghajar, B. Bakkaloglu, T. Thornton

引用次数: 14

A single-chip x-band chirp radar MMIC with stretch processing 单片x波段啁啾雷达MMIC与拉伸处理

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330617

Jianjun Yu, Feng Zhao, Joseph Cali, Desheng Ma, X. Geng, F. Dai, J. Irwin, Andre Aklian

{"title":"A single-chip x-band chirp radar MMIC with stretch processing","authors":"Jianjun Yu, Feng Zhao, Joseph Cali, Desheng Ma, X. Geng, F. Dai, J. Irwin, Andre Aklian","doi":"10.1109/CICC.2012.6330617","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330617","url":null,"abstract":"A single-chip X-band chirp radar transceiver with direct digital synthesis (DDS) for chirp generation is presented. The radar chip, including receiver, transmitter, quadrature DDS, phase-locked loop (PLL) and analog to digital converter (ADC), has been implemented in a 0.13μm BiCMOS technology. The stretch processing technique is employed to translate the time interval between the received and the transmitted chirp signals to a single tone at the baseband output with greatly reduced bandwidth, which allows for the use of a low-cost ADC with a reduced input bandwidth of 10MHz for digitizing the received RF chirp with a bandwidth of 150MHz. A Weaver receiver with a dc-offset is employed in order to use a single ADC for detecting the received quadrature signals with image rejection. A quadrature 1GHz DDS with an inverse sinc function for zero-order hold correction is implemented to provide the chirp signals for both receiver and transmitter. A wide-tuning PLL frequency synthesizer is integrated to generate the local oscillator (LO) signals as well as the clock signal for the DDS and ADC. The implemented radar-on-chip (RoC) MMIC occupies a die area of 3.5 × 2.5mm. With a 2.2V supply voltage for analog/RF and a 1.5V supply for digital, the chip consumes 326mW in the receive mode and 333mW in the transmit mode.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115536250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables 基于对数正态随机变量和的mosfet低频噪声局部变化建模

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330573

Bo Yu, Xin Li, J. Yonemura, Zhiyuan Wu, J. Goo, C. Thuruthiyil, A. Icel

引用次数: 7

A 1.5GHz 0.2psRMS jitter 1.5mW divider-less FBAR ADPLL in 65nm CMOS 基于65nm CMOS的1.5GHz 0.2psRMS抖动1.5mW无分频FBAR ADPLL

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330565

Julie R. Hu, R. Ruby, B. Otis

引用次数: 4

A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing 1mJ/帧统一媒体应用处理器，179.7pJ混合模式特征提取引擎，用于嵌入式3d媒体内容处理

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330650

Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, L. Kim

{"title":"A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing","authors":"Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, L. Kim","doi":"10.1109/CICC.2012.6330650","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330650","url":null,"abstract":"A unified media application processor (UMAP) with a low-power mixed-mode feature extraction engine (FEE) is presented for 2D/3D image analysis/synthesis applications on handheld devices. UMAP supports not only graphics and vision for augmented reality (AR) but also 3D reconstruction and 3D display for 3D-view AR based on heterogeneous many-core platform. A frame-level 3-stage pipelined architecture enables real-time (50fps in VGA) performance in 3D-view AR, while a mixed-mode FEE dynamically saves active power by reconfiguring operation modes between analog and digital processing. Especially for low power operation in media processing, four pairs of analog current contention logics (CCL) are implemented in FEE. The implemented CCL does not require digital-to-analog or analog-to-digital converters (DAC/ADC) in interfacing digital and analog domains. It includes a diode-connected sensing stabilizer which reduces minimum sensing current. Therefore, average power consumed in CCL is reduced by 44.9%. In the implemented UMAP, the proposed FEE replaces the parallel processing core cluster in the analog processing mode, as a result, 96.5% of cluster power and 99.1% of target detection time are saved. The dynamic mode transition between analog and digital processing based on run-time tracking of region-of-interest (ROI) reduces system energy dissipation by up to 84.2% compared to the state-of-the-art embedded media processors.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129754776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 0.791mm2 fully on-chip controller with self-error-correction for boost DC-DC converter based on Zero-Order Control 基于零阶控制的升压DC-DC变换器的0.791mm2自纠错全片上控制器

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330706

Tae-Hwang Kong, Sung-Wan Hong, Sungwoo Lee, Jong-Pil Im, G. Cho

引用次数: 2

A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration 一种0.5V启动87%效率0.75mm2片上前馈单电感双输出(SIDO)升压DC-DC变换器，用于电池和太阳能电池运行传感器网络微型计算机集成

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330632

Y. Nakase, Shin-nosuke Hirose, H. Onoda, Y. Ido, Yoshiaki Shimizu, T. Oishi, T. Kumamoto, Toru Shimizu

引用次数: 9

A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology 采用45纳米CMOS技术的0.65V嵌入式SDRAM，具有智能升压和电源管理功能

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330622

S. Pyo, Jun-Sung Kim, Jung-Han Kim, Hyuntaek Jung, T. Song, Cheol-Ha Lee, Gyu-Hong Kim, Young-Keun Lee, Kee Sup Kim

引用次数: 1