{"title":"A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 μm CMOS technology","authors":"Han Peng, David I. Anderson, M. Hella","doi":"10.1109/CICC.2012.6330631","DOIUrl":null,"url":null,"abstract":"A two-phase four-segment DC-DC converter with novel coupled-inductors output network utilizing phase shedding and phase segmentation is presented for light load efficiency enhancement. The coupled inductor network increases the effective inductance value and reduces inductor current ripple. To improve light load efficiency, resonant gate drivers are employed to reduce driver losses. The DC-DC converter is implemented in 0.18 μm six-metal CMOS technology with 5 V devices, and occupies a total area of 7.77 mm2. The converter achieves a peak efficiency of 77.8% at 6 W output with 5% efficiency improvement at 1 V output due to the use of resonant gate drivers. Furthermore, with phase shedding, the converter maintains peak efficiency as the output current varies from 0.1 A to 1.86 A.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2012.6330631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
A two-phase four-segment DC-DC converter with novel coupled-inductors output network utilizing phase shedding and phase segmentation is presented for light load efficiency enhancement. The coupled inductor network increases the effective inductance value and reduces inductor current ripple. To improve light load efficiency, resonant gate drivers are employed to reduce driver losses. The DC-DC converter is implemented in 0.18 μm six-metal CMOS technology with 5 V devices, and occupies a total area of 7.77 mm2. The converter achieves a peak efficiency of 77.8% at 6 W output with 5% efficiency improvement at 1 V output due to the use of resonant gate drivers. Furthermore, with phase shedding, the converter maintains peak efficiency as the output current varies from 0.1 A to 1.86 A.