A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 μm CMOS technology

Han Peng, David I. Anderson, M. Hella
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引用次数: 8

Abstract

A two-phase four-segment DC-DC converter with novel coupled-inductors output network utilizing phase shedding and phase segmentation is presented for light load efficiency enhancement. The coupled inductor network increases the effective inductance value and reduces inductor current ripple. To improve light load efficiency, resonant gate drivers are employed to reduce driver losses. The DC-DC converter is implemented in 0.18 μm six-metal CMOS technology with 5 V devices, and occupies a total area of 7.77 mm2. The converter achieves a peak efficiency of 77.8% at 6 W output with 5% efficiency improvement at 1 V output due to the use of resonant gate drivers. Furthermore, with phase shedding, the converter maintains peak efficiency as the output current varies from 0.1 A to 1.86 A.
基于0.18 μm CMOS技术的100mhz两相四段DC-DC轻负载效率增强变换器
为了提高轻载效率,提出了一种新型耦合电感输出网络的两相四段DC-DC变换器。耦合电感网络增加了有效电感值,减小了电感电流纹波。为了提高轻载效率,采用了谐振栅极驱动器来减少驱动器损耗。该DC-DC变换器采用0.18 μm六金属CMOS技术,采用5v器件,总面积为7.77 mm2。该变换器在6w输出时达到77.8%的峰值效率,在1v输出时由于使用谐振栅极驱动器,效率提高了5%。此外,随着相位脱落,当输出电流从0.1 A到1.86 A变化时,变换器保持峰值效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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