Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

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A 17pJ/bit 915MHz 8PSK/O-QPSK transmitter for high data rate biomedical applications 用于高数据速率生物医学应用的17pJ/bit 915MHz 8PSK/O-QPSK发射机
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330560
Mehran M. Izad, C. Heng
{"title":"A 17pJ/bit 915MHz 8PSK/O-QPSK transmitter for high data rate biomedical applications","authors":"Mehran M. Izad, C. Heng","doi":"10.1109/CICC.2012.6330560","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330560","url":null,"abstract":"A 915MHz 8PSK/O-QPSK transmitter for high data rate biomedical applications is presented in this paper. The transmitter architecture is based on a sub-harmonic injection-locked ring oscillator and a direct modulated power amplifier to simplify the architecture and reduce the power consumption while achieving spectral efficient modulation. The spurious performance of the injection-locked ring oscillator and the impact of circuit non-idealities on the transmitter performance are also discussed. Fabricated prototype in 65nm CMOS consumes only 938μW at the data rate of 55Mbps and achieves energy efficiency of 17pJ/bit which is the lowest reported to date. The chip occupies an active area of 0.038mm2. The measured EVM is better than 3.8% in 8PSK mode (at 55Mbps) while delivering -15dBm of output power.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127642099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS 在90nm CMOS中嵌入DFE的6b 1.6GS/s冗余周期1抽头ADC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330582
E. Z. Tabasy, Ayman Shafik, S. Huang, N. Yang, S. Hoyos, S. Palermo
{"title":"A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS","authors":"E. Z. Tabasy, Ayman Shafik, S. Huang, N. Yang, S. Hoyos, S. Palermo","doi":"10.1109/CICC.2012.6330582","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330582","url":null,"abstract":"Serial link receivers with ADC front-ends are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6b 1.6GS/s ADC with a novel embedded DFE structure. Leveraging a time-interleaved SAR ADC architecture, a redundant cycle loop-unrolled technique is proposed in order to relax the DFE feedback critical path delay with low power/area overhead. Fabricated in an LP 90nm CMOS process, the 6b ADC with embedded 1-tap DFE consumes 20mW total power, including front-end T/Hs and reference buffers, and the core time-interleaved ADC occupies 0.24mm2 area.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115515386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Behavioral modeling for RF and AMS 射频和AMS的行为建模
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330641
C. McAndrew, Brian Q. Chen
{"title":"Behavioral modeling for RF and AMS","authors":"C. McAndrew, Brian Q. Chen","doi":"10.1109/CICC.2012.6330641","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330641","url":null,"abstract":"The continued increase in functionality and complexity of integrated circuits, especially the integration of analog and RF circuit blocks along with large amounts of digital circuitry, has increased the need for efficient simulation of large analog/mixed-signal (AMS) circuits. This is especially difficult and time-consuming for top-level verification, and for accurate simulation of the nonlinear behavior of high power RF circuits. This session includes three papers that address recent developments in modeling and simulation that expand the scope and improve the accuracy of models and simulation techniques for modern RF transistors and for large AMS systems.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116911422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A unified model and direct extraction methodologies of various CPWs for CMOS mm-wave applications CMOS毫米波应用中各种cpw的统一模型和直接提取方法
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330676
Jun Luo, Lei Zhang, Yan Wang
{"title":"A unified model and direct extraction methodologies of various CPWs for CMOS mm-wave applications","authors":"Jun Luo, Lei Zhang, Yan Wang","doi":"10.1109/CICC.2012.6330676","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330676","url":null,"abstract":"In this paper, a novel unified model for various CPWs, including standard coplanar waveguides (CPW), grounded CPW (GCPW), CPW with slotted shield (SCPW), and corresponding direct extraction methodologies are proposed and investigated. In the SPICE-compatible model, a new C-L-R series path in the parallel branch is introduced to describe the electromagnetic coupling for CPWs with large lower ground or shield, while other kinds of high frequency effects including substrate loss, and skin effect are considered to explain the frequency-dependent per-unit-length Lx, Cx, Rx, and Gx parameters. The direct extraction procedure are established which can ensure both accuracy and simplicity compared with other reported methods. The model is verified by IBM 90nm CMOS processes with SLOT de-embedding techniques. Excellent agreement between the model and the measured data for different CPWs is achieved up to 67GHz. The direct extraction methodologies ensure the feasibility and availability of scalable modeling of CPWs for circuit designer.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"44 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128616439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation 14.5 fJ/cycle/k门,0.33 V的45nm CMOS心电处理器,采用统计误差补偿
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330670
R. Abdallah, Naresh R Shanbhag
{"title":"A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation","authors":"R. Abdallah, Naresh R Shanbhag","doi":"10.1109/CICC.2012.6330670","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330670","url":null,"abstract":"A subthreshold ECG processor in IBM 45 nm SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is employed to further reduce energy (Emin) at the MEOP. SEC is shown to reduce Emin by 28% compared to the conventional (error-free) case while maintaining acceptable beat-detection performance. SEC enables the supply voltage to be scaled to 15% below its critical value at MEOP, while compensating for a 58% pre-correction error rate pe. These results represent an improvement of 19× in beat-detection performance, and 600× in pe over conventional (error-free) systems. The prototype IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energy efficiency than the state-of-the-art while tolerating 16× more voltage variations.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129349533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion 一个10位1-GS/s CMOS ADC, FOM = 70 fJ/转换
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330607
S. Hashemi, B. Razavi
{"title":"A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion","authors":"S. Hashemi, B. Razavi","doi":"10.1109/CICC.2012.6330607","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330607","url":null,"abstract":"A pipelined ADC incorporates a precharged resistor-ladder DAC in a multi-bit front-end, achieving fast settling and allowing calibration of both dynamic and static gain errors. Using simple differential pairs with a gain of 5 as op amps and realized in 65-nm CMOS technology, the 10-bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibits an SNDR of 52.7 dB at an input frequency of 490 MHz.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Compact and behavioral modeling of transistors from NVNA measurements: New flows and future trends NVNA测量晶体管的紧凑和行为建模:新趋势和未来趋势
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330642
D. Root, Jianjun Xu, F. Sischka, M. Marcu, J. Horn, R. M. Biernacki, M. Iwamoto
{"title":"Compact and behavioral modeling of transistors from NVNA measurements: New flows and future trends","authors":"D. Root, Jianjun Xu, F. Sischka, M. Marcu, J. Horn, R. M. Biernacki, M. Iwamoto","doi":"10.1109/CICC.2012.6330642","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330642","url":null,"abstract":"This paper reviews three modern transistor modeling flows enabled by large-signal waveform and/or X-parameter1 measurements from a commercially available nonlinear vector network analyzer (NVNA) instrument. NVNA transistor characterization more safely exercises the device over a wider operating domain than is possible with conventional DC and linear S-parameter measurements, is more indicative of the device large-signal response in actual use conditions, provides data at much faster timescales than pulsed I-V methods, and provides large-signal model validation as a free additional benefit. In the first flow considered, NVNA waveform data is used as a target to extract and tune compact model parameter values and for model validation under large-signal conditions. In the second flow, NVNA waveform data is used to directly construct the multi-variate nonlinear current-source and charge-based nonlinear capacitor functions of an advanced electrothermal and trap-dependent compact model suitable for GaAs and GaN FETs, effectively bypassing the need for explicit model constitutive relation formulation. The final approach is based on the X-parameter measurement and behavioral modeling framework supported by the NVNA, producing nonlinear transistor models directly in the frequency domain. Recent advances in X-parameter methods for transistors, including simple scalability with geometry, show early potential for useful device models, under certain conditions, without the requirement of specifying an internal topology or equivalent circuit at all.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130519307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage 7.5Vmax任意波形发生器,采用65nm标准CMOS,电源电压为1.2V
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330703
T. Nakura, Y. Mita, T. Iizuka, K. Asada
{"title":"7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage","authors":"T. Nakura, Y. Mita, T. Iizuka, K. Asada","doi":"10.1109/CICC.2012.6330703","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330703","url":null,"abstract":"This paper presents a digitally controlled arbitrary waveform generator whose output voltage range is 0 to 7.5V under a 1.2V supply voltage. The high output voltage generation is realized using only 65nm standard MOS transistors. It consists of a voltage increasing block and a voltage decreasing block to realize stable high voltage output. Experimental results show that our waveform generator can generate arbitrary waveform, and it directly drives a MEMS structure.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130560518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration 一个12位50 ms /s 3.3 mw SAR ADC,带有背景数字校准
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330694
Wenbo Liu, P. Huang, Y. Chiu
{"title":"A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration","authors":"Wenbo Liu, P. Huang, Y. Chiu","doi":"10.1109/CICC.2012.6330694","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330694","url":null,"abstract":"This paper describes a background digital calibration technique based on bitwise correlation (BWC) to correct the capacitive digital-to-analog converter (DAC) mismatch error in successive-approximation-register (SAR) analog-to-digital converters (ADC's). Aided by a single-bit pseudorandom noise (PN) injected to the ADC input, the calibration engine extracts all bit weights simultaneously to facilitate a digital-domain correction. The analog overhead associated with this technique is negligible and the conversion speed is fully retained (in contrast to [1] in which the ADC throughput is halved). A prototype 12bit 50-MS/s SAR ADC fabricated in 90-nm CMOS measured a 66.5-dB peak SNDR and an 86.0-dB peak SFDR with calibration, while occupying 0.046 mm2 and dissipating 3.3 mW from a 1.2-V supply. The calibration logic is estimated to occupy 0.072 mm2 with a power consumption of 1.4 mW in the same process.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling 0.5V, 11.3 μ w, 1-kS/s电阻传感器接口电路,相关双采样
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330702
Hyunsoo Ha, Yunjae Suh, Seon-Kyoo Lee, Hong-June Park, J. Sim
{"title":"A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling","authors":"Hyunsoo Ha, Yunjae Suh, Seon-Kyoo Lee, Hong-June Park, J. Sim","doi":"10.1109/CICC.2012.6330702","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330702","url":null,"abstract":"This paper presents a low-power resistive sensor interface circuit with correlated double sampling which reduces the effect of amplifier offset and enables time-interleaved single-to-differential sampling. The proposed sampling scheme, used with a 12b SAR-type analog-to-digital converter, effectively doubles the input signal and improves linearity. The fabricated chip in 0.13μm CMOS demonstrates a sampling rate of 1-kS/s and a dynamic range of 117dB with a maximum conversion error of 0.32-percent while consuming only 11.3-μW from single supply voltage of 0.5V.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123365150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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