A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion

Abstract

A pipelined ADC incorporates a precharged resistor-ladder DAC in a multi-bit front-end, achieving fast settling and allowing calibration of both dynamic and static gain errors. Using simple differential pairs with a gain of 5 as op amps and realized in 65-nm CMOS technology, the 10-bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibits an SNDR of 52.7 dB at an input frequency of 490 MHz.