A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS

Abstract

Serial link receivers with ADC front-ends are emerging in order to scale data rates over high attenuation channels. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-efficient receiver. This paper presents a 6b 1.6GS/s ADC with a novel embedded DFE structure. Leveraging a time-interleaved SAR ADC architecture, a redundant cycle loop-unrolled technique is proposed in order to relax the DFE feedback critical path delay with low power/area overhead. Fabricated in an LP 90nm CMOS process, the 6b ADC with embedded 1-tap DFE consumes 20mW total power, including front-end T/Hs and reference buffers, and the core time-interleaved ADC occupies 0.24mm2 area.