Proceedings of the IEEE 2012 Custom Integrated Circuits Conference最新文献

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A Full-Band processor for reduction of RF mixer LO harmonic images 用于降低射频混频器LO谐波图像的全频带处理器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330614
R. Gomez, H. Zou, B. Chen, B. Currivan, D. Chang
{"title":"A Full-Band processor for reduction of RF mixer LO harmonic images","authors":"R. Gomez, H. Zou, B. Chen, B. Currivan, D. Chang","doi":"10.1109/CICC.2012.6330614","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330614","url":null,"abstract":"A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm2 and uses 205 mW.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation SpiNNaker:用于大规模并行神经网络仿真的多核片上系统
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330636
E. Painkras, L. Plana, J. Garside, S. Temple, Simon Davidson, J. Pepper, David M. Clark, Cameron Patterson, S. Furber
{"title":"SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation","authors":"E. Painkras, L. Plana, J. Garside, S. Temple, Simon Davidson, J. Pepper, David M. Clark, Cameron Patterson, S. Furber","doi":"10.1109/CICC.2012.6330636","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330636","url":null,"abstract":"The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129570480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
Linearization of class D amplifiers D类放大器的线性化
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330567
P. Balmelli, J. Khoury, Eduardo Viegas, Paulo Santos, V. Pereira
{"title":"Linearization of class D amplifiers","authors":"P. Balmelli, J. Khoury, Eduardo Viegas, Paulo Santos, V. Pereira","doi":"10.1109/CICC.2012.6330567","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330567","url":null,"abstract":"Signal dependent propagation delay and supply modulation are among the major sources of performance deterioration in class D amplifiers. More so in the case where the control of the common-mode EMI of a Class D amplifier utilizes DSP-based signal spreading techniques and requires the switching amplifier to be “linear” to avoid folding the high frequency spectrum into the audio band. This paper reviews the sources of nonlinearity and describes two original solutions based on analog feedback techniques for a 3W audio amplifier that were implemented in a 110 nm CMOS process.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127876802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization of Inverse Temperature Dependence in logic circuits 逻辑电路中逆温度依赖性的表征
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330659
M. Cho, M. Khellah, Kwanyeob Chae, K. Z. Ahmed, J. Tschanz, S. Mukhopadhyay
{"title":"Characterization of Inverse Temperature Dependence in logic circuits","authors":"M. Cho, M. Khellah, Kwanyeob Chae, K. Z. Ahmed, J. Tschanz, S. Mukhopadhyay","doi":"10.1109/CICC.2012.6330659","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330659","url":null,"abstract":"As the supply voltage (VDD) approaches the device threshold voltage (VT), the elevated temperature results in increased device current. This phenomenon is generally known as Inverse Temperature Dependence (ITD). In this paper, we propose a test structure with a built-in poly-resistor-based heater to characterize ITD in digital circuits. Our measurements from a 130nm test-chip show that the Zero-Temperature-Coefficient (ZTC) point varies by circuit type, and further fluctuates due to process variation. A more accurate ITD-sensitive thermal sensor is thus needed for better temperature tracking.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124610021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation 一种用于硅前和硅后电验证的混合电行为建模方法
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330559
N. Hakim, A. Bhaduri, K. Donepudi, S. Bodapati
{"title":"A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation","authors":"N. Hakim, A. Bhaduri, K. Donepudi, S. Bodapati","doi":"10.1109/CICC.2012.6330559","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330559","url":null,"abstract":"This paper discusses pre- and post-silicon electrical validation requirements for highly integrated designs and highlights the need for large-scale modeling and simulation of analog components in the context of validation. Current fast SPICE tools and Analog-Mixed Signal simulation do not provide the speed and scalability necessary to perform full cluster or system-level verification of high-speed IO links or to perform a variability analysis of these circuits. This paper outlines a method to scale the simulation of these circuits with correct accounting of voltage and temperature fluctuations, within-die and die-to-die variations, and platform uncertainty, with little loss in accuracy. The results are illustrated on a self-biased PLL example and illustrate the tremendous speedup that can be achieved while maintaining a comparable accuracy to SPICE for the behaviors that are modeled.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116310705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS 在65nm CMOS电流参考预充电过零管道- sar ADC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330701
J. Kuppambatti, P. Kinget
{"title":"A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS","authors":"J. Kuppambatti, P. Kinget","doi":"10.1109/CICC.2012.6330701","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330701","url":null,"abstract":"Using a current reference pre-charge technique, the need for power hungry low impedance voltage reference buffers is eliminated in a zero-crossing pipeline-SAR ADC. The 40MS/s ADC prototype, implemented in a 65nm CMOS process, achieves an SFDR/SDR/SNDR of 70dB/66dB/59.5dB at Nyquist, while occupying 0.95mm2 and consuming 4.5mW from a 1.35V supply, requiring no additional power for reference buffers.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127149280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A feedback controlled coil driver for transcutaneous power transmission 一种用于经皮电力传输的反馈控制线圈驱动器
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330600
Edward K. F. Lee
{"title":"A feedback controlled coil driver for transcutaneous power transmission","authors":"Edward K. F. Lee","doi":"10.1109/CICC.2012.6330600","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330600","url":null,"abstract":"A fully integrated feedback controlled coil driver for transcutaneous power transmission was proposed to power biomedical implants. For a normal power transmission operation, the voltage across the switch that energizes the coil is sampled and compared with ground, followed by an integration to obtain an optimal on-time for the switch such that the coil current was maximized for a given DC input power. The coil driver also provides ASK modulation on the coil current by changing the size of the switch according to the input data. In the normal power transmission operation, a peak-to-peak coil current of ~730mA was obtained with a power dissipation of 71.6mW at 5V.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130690857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS 10Gb/s 10mW双抽头可重构的65nm LP CMOS预强调发射机
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330581
Yue Lu, Kwangmo Jung, Y. Hidaka, E. Alon
{"title":"A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS","authors":"Yue Lu, Kwangmo Jung, Y. Hidaka, E. Alon","doi":"10.1109/CICC.2012.6330581","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330581","url":null,"abstract":"A low-power pre-emphasis voltage mode transmitter architecture with output swing control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only ~10mW from a 1.2V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-tap pre-emphasis, achieving 1pJ/bit energy efficiency.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131962943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS 基于0.13μm CMOS的160mV 670nW 8位SAR ADC
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330693
Xiong Zhou, Qiang Li
{"title":"A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS","authors":"Xiong Zhou, Qiang Li","doi":"10.1109/CICC.2012.6330693","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330693","url":null,"abstract":"An 8-bit SAR ADC capable of working under 160mV supply voltage is presented. To facilitate the ultra-low voltage comparator, a novel inverter-based amplifier is proposed and a dynamic latch with both gate and bulk driven input is exploited. An improved switching technique utilizing clock boosting and device stacking is employed for the ultra-low voltage sampling network. Implemented in a 0.13μm CMOS, the fabricated ADC works from 40kS/s to 400kS/s sampling rate under 160mV to 300mV supply voltage, respectively. Drawing 670nW from a single 160mV supply, the ADC achieves 0.5LSB DNL, 0.62LSB INL, 61.1dB SFDR and 7.3bit ENOB at a near-Nyquist input frequency of 19.7 kHz. To the best of authors' knowledge, this is one of the lowest reported supply voltages in analog design.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128029412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
22-nm fully-depleted tri-gate CMOS transistors 22nm全耗尽三栅极CMOS晶体管
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Pub Date : 2012-10-15 DOI: 10.1109/CICC.2012.6330657
C. Auth
{"title":"22-nm fully-depleted tri-gate CMOS transistors","authors":"C. Auth","doi":"10.1109/CICC.2012.6330657","DOIUrl":"https://doi.org/10.1109/CICC.2012.6330657","url":null,"abstract":"At the 22-nm technology node, fully-depleted tri-gate transistors were introduced for the first time on a high-volume manufacturing process. Fabricated on a bulk silicon substrate, these transistors feature a third-generation high-k + metal-gate technology and a fifth generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (~70 mV/decade) and very low DIBL (~50 mV/V) values that are critical for low voltage operation. Self-aligned contacts are implemented along with the tri-gate transistors to eliminate restrictive contact-to-gate registration requirements from scaling the gate pitch. This enables an SRAM cell size of 0.092 μm2. High yield and reliability have been demonstrated on multiple microprocessors.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115361363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 139
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