J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, Michael P. Beakes, J. Tierno, D. Friedman
{"title":"一个基于45nm SOI CMOS的3.2GS/s 4.55b ENOB两步分位ADC","authors":"J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, Michael P. Beakes, J. Tierno, D. Friedman","doi":"10.1109/CICC.2012.6330610","DOIUrl":null,"url":null,"abstract":"A 3.2GS/s two-step subranging ADC is implemented in a 45nm SOI-CMOS technology. The measured ENOB is 4.55b at 1.6GHz. The IIP3 is -1.1dBm. The power consumption is 22mW from a 1.05V voltage supply for a FOM of 290fJ/ conversion-step. The chip occupies an active area of 0.07mm2.","PeriodicalId":130434,"journal":{"name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS\",\"authors\":\"J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, Michael P. Beakes, J. Tierno, D. Friedman\",\"doi\":\"10.1109/CICC.2012.6330610\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3.2GS/s two-step subranging ADC is implemented in a 45nm SOI-CMOS technology. The measured ENOB is 4.55b at 1.6GHz. The IIP3 is -1.1dBm. The power consumption is 22mW from a 1.05V voltage supply for a FOM of 290fJ/ conversion-step. The chip occupies an active area of 0.07mm2.\",\"PeriodicalId\":130434,\"journal\":{\"name\":\"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2012.6330610\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2012.6330610","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
A 3.2GS/s two-step subranging ADC is implemented in a 45nm SOI-CMOS technology. The measured ENOB is 4.55b at 1.6GHz. The IIP3 is -1.1dBm. The power consumption is 22mW from a 1.05V voltage supply for a FOM of 290fJ/ conversion-step. The chip occupies an active area of 0.07mm2.