A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction

Abstract

A low power and very low area 10-bit 220MS/s SAR ADC is presented. The ADC employs a redundancy scheme that relaxes the DAC settling requirement and enables high sample rates, as well as a digital metastability identification and correction algorithm that exploits the redundancy as an error-correction code. The proposed ADC was implemented in CMOS 65nm, and takes up only 0.015mm2. At 220MS/s it consumes 4.3mW and achieves 51.7dB SNDR for a full scale sinusoidal input. For OFDM-like signals (wide-band 13dB Peak-to-RMS) the equivalent ENOB is 9.1 bit at 220MS/s. The figure-of-merit (FOM) is 63fJ/(conversion-step) at 220MS/s and 43fJ/conv-step at 160Ms/s.