Soon-Kyun Shin, J. Rudell, D. Daly, C. Muñoz, D. Chang, K. Gulati, Hae-Seung Lee, M. Straayer
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A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS
A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFDR with a 99.6MHz input signal at 200MS/s are achieved for a FOM of 131fJ/step. The reference buffer, bias circuitry, and digital error correction circuits are all implemented on chip.
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