Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs)

Abstract

This paper presents an overview of design and manufacturing readiness for silicon interposer based 3D integration. We present a field programmable gate array research and development vehicle to demonstrate the capabilities of 3D technology. The characterization results show minimal performance impact due to through silicon via (TSV) to 10Gbps transceivers and potential improvement in performance by integrating metal-insulator-metal (MIM) capacitor on silicon interposer. We also provide an overview of various process steps involved in the creation and integration of TSV on silicon interposer and methods to optimize them for performance and cost. Cost reduction can be achieved by process optimization at an integrated or holistic level, better alignment of interposer specification with application requirements, and die-package co-design.