A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers

Atsutake Kosuge, Wataru Mizuhara, N. Miura, M. Taguchi, H. Ishikuro, T. Kuroda
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引用次数: 8

Abstract

A reduced-reflection multi-drop bus system using Dicode (1-D) partial response signaling transceiver is presented for the first time in the world. Directional couplers on transmission lines arranged with equi-energy distributing and exact impedance matched conditions allow the bus to reach to 12.5Gbps/link speed. The transmission line has 5-convex portions to form one side of a coupler where the transmission line width is adjusted to control the characteristic impedance of the coupling section, minimizing signal reflection from each section. Dicode partial-response signaling method with a half-rate architecture was used where a precoder is placed in the transmitter to make the signal best fit for the channel to eliminate inter symbol interference (ISI) where the test chip transmitter occupies 3,750 μm2 and the receiver occupies 750 μm2 with 90nm CMOS technology, consuming 40mA and 23mA respectively at the supply voltage of 1.2V.
采用阻抗匹配传输线耦合器和Dicode部分响应通道收发器的12.5Gb/s/链路非接触多滴总线系统
在国际上首次提出了一种采用Dicode (1-D)部分响应信令收发器的减反射多滴总线系统。传输线上定向耦合器按等能量分布和精确阻抗匹配条件布置,使总线达到12.5Gbps/链路速度。传输线具有5个凸部分,以形成耦合器的一侧,其中调整传输线宽度以控制耦合部分的特性阻抗,使来自每个部分的信号反射最小化。采用半速率结构的双码部分响应信令方法,在发射机中放置预编码器,使信号最适合信道,消除码间干扰(ISI),测试芯片发射机占地3750 μm2,接收机占地750 μm2,采用90nm CMOS技术,在1.2V供电电压下分别消耗40mA和23mA。
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