A. Paul, Matt Amrein, Saket Gupta, Arvind Vinod, A. Arun, S. Sapatnekar, C. Kim
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Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors
In order to reduce the impact of resonant supply noise on processor performance, a simple, fully-digital and scalable technique based on staggering the activation time of the cores sharing the same power domain in a multi-core multi-power domain processor is presented. Measurement data from a 65nm test chip shows an Fmax improvement as large as 20% in a 3-core configuration. This is one of the first approaches to utilize the architecture level behavior for mitigating resonant noise issues in a multi-core multi-power domain processor.
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