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A 130nm RFSOI technology with switch, LNA, and EDNMOS devices for integrated front-end module SoC applications 130nm RFSOI技术与开关，LNA和EDNMOS器件集成前端模块SoC应用
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337701
Raj Verma Purakh, Shaoqiang Zhang, Rui Tze Toh, J. S. Wong, Gao Wei, K. Chew, R. Nair, D. Harame, J. Watts, T. Mckay
{"title":"A 130nm RFSOI technology with switch, LNA, and EDNMOS devices for integrated front-end module SoC applications","authors":"Raj Verma Purakh, Shaoqiang Zhang, Rui Tze Toh, J. S. Wong, Gao Wei, K. Chew, R. Nair, D. Harame, J. Watts, T. Mckay","doi":"10.1109/RFIC.2015.7337701","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337701","url":null,"abstract":"The cellular frequency spectrum has become increasingly complex with over 50 frequencies in LTE standards. To reduce costs in the front end module the switch has migrated from a III-V PHEMT base to a silicon solution in RFSOI. While many providers have focused on a 180nm base technology node for the RFSOI there has been an increasing move to more advanced nodes to solution the logic requirements of the cellular standards. In addition there has been a strong interest in migrating to an SOC solution in RFSOI. In this paper a 130nm RFSOI technology is presented with high performance and low noise body tied 1.5V NMOS for LNA devices with a novel method of body contacting, low Ron*Coff NMOS for antenna switch and state of the art EDNMOS with fT of 38GHz and BVdss of 14V BVdss for integrated PA application. Specific results presented include characterization of the switch, LNA, and Power Amplifier devices.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130367049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS technology with autonomic NF calibration 18mW, 3.3dB NF, 60GHz LNA，采用32nm SOI CMOS技术，具有自主NF校准功能
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337769
J. Plouchart, F. Wang, A. Balteanu, B. Parker, M. Sanduleanu, M. Yeck, V. H. Chen, W. Woods, B. Sadhu, A. Valdes-Garcia, X. Li, D. Friedman
{"title":"A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS technology with autonomic NF calibration","authors":"J. Plouchart, F. Wang, A. Balteanu, B. Parker, M. Sanduleanu, M. Yeck, V. H. Chen, W. Woods, B. Sadhu, A. Valdes-Garcia, X. Li, D. Friedman","doi":"10.1109/RFIC.2015.7337769","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337769","url":null,"abstract":"A self-healing mmWave SoC integrating an 8052 microcontroller with 12kB of memory, an ADC, a temperature sensor, and a 3-stage cascode 60GHz LNA, implemented in a 32nm SOI CMOS technology exhibits a peak gain of 21dB, an average 3.3dB NF from 53 to 62GHz and 18mW power consumption. An indirect NF sensing algorithm was implemented on the integrated uC, which enables an adaptive biasing algorithm to reduce the 60GHz NF sigma and LNA power consumption by 37 and 40%, respectively, across P,V,T.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116601409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A Class-C self-mixing-VCO architecture with high tuning-range and low phase-noise for mm-wave applications 具有高调谐范围和低相位噪声的c类自混频vco结构，适用于毫米波应用
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337716
A. H. M. Shirazi, Amir Nikpaik, Reza Molavi, S. Mirabbasi, S. Shekhar
{"title":"A Class-C self-mixing-VCO architecture with high tuning-range and low phase-noise for mm-wave applications","authors":"A. H. M. Shirazi, Amir Nikpaik, Reza Molavi, S. Mirabbasi, S. Shekhar","doi":"10.1109/RFIC.2015.7337716","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337716","url":null,"abstract":"Achieving high tuning-range and low phase-noise simultaneously in mm-wave voltage-controlled oscillators (VCO) has been a severe design challenge. Our architecture, referred herein as a self-mixing VCO (SMV), utilizes a Class-C push-push VCO topology to generate the first (f0) and second harmonics (2f0) and then mixes them together to obtain the desired third harmonic (3f0) component. Compared to a fundamental-mode VCO operating at 3f0 in mm-wave band, the SMV architecture achieves superior frequency tuning range (FTR) and phase-noise (PN) performance. A Class-C topology enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance and reduces phase noise. A 52.8-to-62.5 GHz SMV prototype is designed and implemented in a 0.13-μm CMOS process. Measurement results show an FTR of 16.8% together with a PN of -100.57 dBc/Hz at 1 MHz offset - resulting in an FTR-inclusive figure-of-merit (FOMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply voltage.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129599892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The MATRICs RF-FPGA in 180nm SiGe-on-SOI BiCMOS 矩阵射频fpga在180nm sigon - soi BiCMOS
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337760
L. Kushner, Kevin Sliech, G. Flewelling, Joseph Cali, C. Grens, S. E. Turner, D. Jansen, J. L. Wood, Gary M. Madison
{"title":"The MATRICs RF-FPGA in 180nm SiGe-on-SOI BiCMOS","authors":"L. Kushner, Kevin Sliech, G. Flewelling, Joseph Cali, C. Grens, S. E. Turner, D. Jansen, J. L. Wood, Gary M. Madison","doi":"10.1109/RFIC.2015.7337760","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337760","url":null,"abstract":"MATRICs (Microwave Array Technology for Reconfigurable Integrated Circuits) is a DC-to-20 GHz general purpose reconfigurable array of RF circuits embedded in a flexible switch fabric. Fabricated in a commercial SiGe-on-SOI BiCMOS process, the MATRICs IC employs SiGe HBTs for high-linearity (> + 10 dBm IIP3) amplification and low phase-noise frequency generation, and SOI FETs for low-loss switching. It achieves high on-chip RF isolation (>80 dB at 16 GHz) due to the high-resistivity SOI substrate, differential signalling, and chip-scale flip-chip bump packaging. MATRICs will allow fixed-function RF systems to have the size, weight, and power benefits of a custom RF ASIC without the associated long development cycle and high NRE, and enable future RF subsystems to be dynamically reconfigured on-the-fly, adapting to changing environments.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134242565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Power supply bypass capacitors—Myths and realities 电源旁路电容器——神话与现实
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337791
W. Kuhn, Andrew D. Fund
{"title":"Power supply bypass capacitors—Myths and realities","authors":"W. Kuhn, Andrew D. Fund","doi":"10.1109/RFIC.2015.7337791","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337791","url":null,"abstract":"Power supply bypass capacitors are critical to the operation of high-frequency analog and digital circuits, yet are seldom considered in the depth they deserve. This paper investigates their use and the resulting power integrity effects as seen from an RFIC bondpad looking out to a host PCB. We show how designs can be either successful or unsuccessful depending on the capacitor values selected and the frequencies involved. In particular, the common practice of placing two or three graduated-size capacitors in an attempt to create a broadband AC ground may actually be counterproductive and potentially damaging to circuit operation. The associated problem of placing partial bypassing on-chip with larger bypass capacitors off-chip is also studied and guidance for avoiding hidden dangers is given.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133514337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3–10mW, 3.1–10.6GHz integer-N QPLL with reference spur reduction technique for UWB-based cognitive radios 基于超宽带认知无线电的3-10mW、3.1-10.6GHz整数n QPLL参考杂散抑制技术
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337706
Nam-Seog Kim, J. Rabaey
{"title":"A 3–10mW, 3.1–10.6GHz integer-N QPLL with reference spur reduction technique for UWB-based cognitive radios","authors":"Nam-Seog Kim, J. Rabaey","doi":"10.1109/RFIC.2015.7337706","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337706","url":null,"abstract":"An integer-N charge pump QPLL provides 3.168 - 10.56GHz lock range, -108.38dBc/Hz phase noise at 1MHz offset, and -59.42dBc reference spur with digital calibration technique for charge pump mismatch while consuming 10.1mW at 10.56GHz with 4-divder at the output. A wideband low power TSPC programmable divider supports 57 sub-bands. It is implemented in a 1V 65nm CMOS process. Active area is 0.12mm2.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114884025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 16-element W-band phased array transceiver chipset with flip-chip PCB integrated antennas for multi-gigabit data links 一种16元w波段相控阵收发器芯片组，具有用于多千兆数据链路的倒装PCB集成天线
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337696
S. Shahramian, M. Holyoak, Y. Baeyens
{"title":"A 16-element W-band phased array transceiver chipset with flip-chip PCB integrated antennas for multi-gigabit data links","authors":"S. Shahramian, M. Holyoak, Y. Baeyens","doi":"10.1109/RFIC.2015.7337696","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337696","url":null,"abstract":"This paper describes the design and implementation of a W-band phased array system with integrated PCB antennas capable of multi-gigabit spectrally-efficient wireless communication. The chipset is manufactured in a 0.18μm SiGe BiCMOS technology with fT/fMAX of 240/270GHz and is flip-chipped onto an organic PCB with integrated antenna arrays. Each chip is equipped with 16-transmit/4-receive or 16-receive/4-transmit calibrated phase shifter elements, direct up- and down-converters plus a half-rate phase locked loop. Each transceiver IC operates from 1.5V and 2.5V supplies and consumes 5.5W and 4.5W in transmit and receive mode respectively. The transmitter EIRP is 34dBm in each polarization. A 4.8Gb/s QPSK wireless link in each polarization is demonstrated at a distance of 20-meters.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114921101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A low-power FSK/OOK transmitter for 915 MHz ISM band 915mhz ISM频段的低功耗FSK/OOK发射机
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337730
M. S. Jahan, Jeremy Langford, J. Holleman
{"title":"A low-power FSK/OOK transmitter for 915 MHz ISM band","authors":"M. S. Jahan, Jeremy Langford, J. Holleman","doi":"10.1109/RFIC.2015.7337730","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337730","url":null,"abstract":"A PLL-based, low-power, 915 MHz FSK/OOK transmitter is presented. The PLL uses gain-boosted LC VCO and hybrid injection-locked divider topologies to reduce power consumption with acceptable phase noise. In FSK mode, the transmitter consumes 367 μW from a 1.2 V supply with -18.6 dBm output power and achieves maximum 3 Mbps speed (122.3 pJ/bit). In OOK, power consumption is 314 μW with maximum 20 Mbps speed (15.7 pJ/bit). The transmitter occupies 0.29 mm2 of die area in a 130 nm CMOS process.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114457135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL 用于ADPLL的103fsrms 1.32mW 50MS/s 1.25MHz带宽两步闪存-ΔΣ时间-数字转换器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337713
Ying Wu, P. Lu, R. Staszewski
{"title":"A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL","authors":"Ying Wu, P. Lu, R. Staszewski","doi":"10.1109/RFIC.2015.7337713","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337713","url":null,"abstract":"A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134275174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 54–84 GHz CMOS SPST switch with 35 dB isolation 54-84 GHz CMOS SPST开关，35 dB隔离
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337693
R. Shu, A. Tang, B. Drouin, Q. Gu
{"title":"A 54–84 GHz CMOS SPST switch with 35 dB isolation","authors":"R. Shu, A. Tang, B. Drouin, Q. Gu","doi":"10.1109/RFIC.2015.7337693","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337693","url":null,"abstract":"This paper presents a hybrid design based, CMOS millimeter-wave (mm-wave) single-polar single-throw (SPST) switch. The circuit design starts from the analysis and optimization of a distributed structure, while implemented using coupled lump elements for performance improvement and area-efficient layout. Moreover, a specific bias scheme is used to further decrease insertion loss by more than 0.5 dB. This SPST switch achieves higher than 35 dB isolation over an ultra-wide frequency range, from 54 GHz to 84 GHz, a minimum 1.7 dB insertion loss, and <;-10 dB return loss with 0.012 mm2 chip area in 65 nm CMOS. This design achieves more than 10 dB enhancement of isolation by comparing with state-of-the-arts while maintaining similar insertion loss.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125987258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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