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A passive-mixer-first receiver with LO leakage suppression, 2.6dB NF, >15dBm wide-band IIP3, 66dB IRR supporting non-contiguous carrier aggregation 无源混频器优先接收器，具有LO泄漏抑制，2.6dB NF， >15dBm宽带IIP3, 66dB IRR，支持非连续载波聚合
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337728
Charles Wu, Yanjie Wang, B. Nikolić, C. Hull
{"title":"A passive-mixer-first receiver with LO leakage suppression, 2.6dB NF, >15dBm wide-band IIP3, 66dB IRR supporting non-contiguous carrier aggregation","authors":"Charles Wu, Yanjie Wang, B. Nikolić, C. Hull","doi":"10.1109/RFIC.2015.7337728","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337728","url":null,"abstract":"A passive-mixer-first receiver design in 28 nm CMOS is presented where the front-end 5-bit mixer DAC provides a wide-band tuneable impedance match to suppress the LO leakage as well as to improve image rejection performance. Baseband LNA together with the AC-boosting compensation amplifier provides a 50MHz baseband bandwidth, which allows support for non-contiguous carrier aggregation for LTE. The proposed design can suppress multiple LO harmonics down below -62dBm. The system achieves <; 3dB NF, >15dBm IIP3 and an IRR > 66dB with 60mW power.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132731617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A wideband envelope-tracking CMOS linear transmitter without digital predistortion 无数字预失真的宽带包络跟踪CMOS线性发射机
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337781
J. Woo, Sunghwan Park, Y. Kwon
{"title":"A wideband envelope-tracking CMOS linear transmitter without digital predistortion","authors":"J. Woo, Sunghwan Park, Y. Kwon","doi":"10.1109/RFIC.2015.7337781","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337781","url":null,"abstract":"In this work, an effective linearization technique to linearize both AM-PM and AM-AM distortions in CMOS envelope tracking (ET) transmitter is developed using dual shaping tables. AM-AM response is linearized using iso-gain shaping table. A variable phase shifter is integrated with the RF power amplifier (RF PA), which linearizes AM-PM response of CMOS ET PA in conjunction with the iso-gain shaping table. In this way, no additional digital predistortion (DPD) is required to linearize the CMOS ET PA. The 2-stage RF PA with the integrated phase compensation circuit is fabricated in 0.28-μm SOI CMOS process. The ET transmitter system demonstrated using the CMOS envelope amplifier (EA) shows an overall system PAE of 42.2% with -34.5 dBc E-UTRA ACLR with 40 MHz BW LTE signal centered at 0.837 GHz. The proposed method overcomes the bandwidth limitation of the conventional methods relying on DPD and/or feedback loops, and can be applied to wide bandwidth LTE signals.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":" 97","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113952611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low cost Ka-band 7W GaAs PHEMT based HPA with GaN PHEMT equivalent performance 具有GaN PHEMT等效性能的低成本ka波段7W GaAs PHEMT HPA
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337741
K. Fujii
{"title":"Low cost Ka-band 7W GaAs PHEMT based HPA with GaN PHEMT equivalent performance","authors":"K. Fujii","doi":"10.1109/RFIC.2015.7337741","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337741","url":null,"abstract":"This paper describes a very low cost MMIC high power amplifier (HPA) with output power of over 7W. The MMIC was fabricated using a GaAs PHEMT process with a state-of-the-art compact die area of 13.7mm2. The HPA MMIC contains a phase and amplitude compensated output power combiner and super low loss phase compensated inter-stage matching networks. A four stage amplifier demonstrated commercially available GaN PHEMT based HPA equivalent performance with 7W saturated output power and 24dB small signal gain from 27.5GHz to 30GHz with peak output power of 8.3W and power added efficiency (PAE) of 27%. This low cost MMIC HPA achieved approximately 10-times lower production cost than GaN PHEMT based MMIC HPAs.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116362340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 5.5-GHz multi-mode power amplifier with reconfigurable output matching network 具有可重构输出匹配网络的5.5 ghz多模功率放大器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337740
Huan-Sheng Chen, Yi-Keng Hsieh, Liang-Hung Lu
{"title":"A 5.5-GHz multi-mode power amplifier with reconfigurable output matching network","authors":"Huan-Sheng Chen, Yi-Keng Hsieh, Liang-Hung Lu","doi":"10.1109/RFIC.2015.7337740","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337740","url":null,"abstract":"A 5.5-GHz multi-mode PA with a reconfigurable output matching network which enables near-optimal impedances for size-scaling MOS transistors is proposed. The required load adaption is realized by using two transformers along with stage-bypassing technique for impedance coarse tuning and a switched capacitor for impedance fine tuning. Using a 90-nm CMOS process, the proposed PA demonstrates a PAE enhancement of 2.2×, 3.0×, and 5.0× respectively at 6-dB, 9-dB, and 15-dB transmit power back-off.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116375802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Compact broadband amplifiers with up to 105 GHz bandwidth in SiGe BiCMOS 紧凑型宽带放大器，带宽高达105ghz，采用SiGe BiCMOS
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337690
Faisal Ahmed, M. Furqan, K. Aufinger, A. Stelzer
{"title":"Compact broadband amplifiers with up to 105 GHz bandwidth in SiGe BiCMOS","authors":"Faisal Ahmed, M. Furqan, K. Aufinger, A. Stelzer","doi":"10.1109/RFIC.2015.7337690","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337690","url":null,"abstract":"In this paper the design and measurements of a single-ended and a fully differential broadband amplifier are presented. The amplifiers are based on a lumped circuit design topology and are highly compact with an active chip area of around 0.02mm2. The amplifiers are fabricated in a 0.13-μm SiGe BiCMOS HBT technology. Wide bandwidth is achieved with a common-base input stage and an output cascode stage buffered with emitter followers. A 3-dB bandwidth of around 91 GHz and 105 GHz, and a small-signal gain of 13 dB and 12 dB are achieved for the single-ended and the differential-ended amplifiers, respectively. The differential-ended amplifier shows a superior performance with an input return loss greater than 10 dB from DC-110 GHz, ±1 dB in-band gain ripple and a low group delay variation of ±6 psec. Large signal measurements show a single-ended saturated power of around 2.8 dBm.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115148329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
4-terminal Angelov model for SOI CMOS MESFETs SOI CMOS mesfet的4端Angelov模型
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337779
S. Wilk, W. Lepkowski, P. Habibimehr, T. Thornton
{"title":"4-terminal Angelov model for SOI CMOS MESFETs","authors":"S. Wilk, W. Lepkowski, P. Habibimehr, T. Thornton","doi":"10.1109/RFIC.2015.7337779","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337779","url":null,"abstract":"This work describes an improved Angelov/Chalmers MESFET model which includes substrate bias effects. The 4-terminal model employs a new and simplified gate current extraction method based on a forward and reverse diode equation which can be independently modified. The improved model is applied to a silicon metal-semiconductor-field-effect-transistor (MESFET) that was fabricated using a 45nm SOI CMOS process and designed for RF power amplifier applications. The model fits across DC and RF parameters and also shows a good fit to a 2.5GHz load pull measurement used for verification.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114543629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 25.6 dBm wireless transmitter using RF-PWM with carrier switching in 130-nm CMOS 一种25.6 dBm无线发射机，采用RF-PWM和130纳米CMOS载波开关
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337724
Kunhee Cho, R. Gharpurey
{"title":"A 25.6 dBm wireless transmitter using RF-PWM with carrier switching in 130-nm CMOS","authors":"Kunhee Cho, R. Gharpurey","doi":"10.1109/RFIC.2015.7337724","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337724","url":null,"abstract":"A wireless transmitter using RF pulse-width-modulation (PWM) with carrier switching is introduced. The proposed approach overcomes the dynamic range limitation of PWM at radio frequencies by utilizing carrier switching between fundamental and half-fundamental frequencies, depending on the signal level to be transmitted. This allows for transmission of signals with large peak-to-average power ratio (PAPR) such as OFDM. The efficiency is also improved in the power back-off region due to reduced switching losses in the half-fundamental mode. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 64-QAM OFDM signals, the average output power is 18.3 dBm and the PAE is 16% with an EVM of -25.5 dB.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128093302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer 一种基于0.7至24 GHz分数n合成器的电容增强全倍频程LC压控振荡器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337717
B. Sadhu, M. Ferriss, D. Friedman
{"title":"A capacitance boosted full-octave LC VCO based 0.7 to 24 GHz fractional-N synthesizer","authors":"B. Sadhu, M. Ferriss, D. Friedman","doi":"10.1109/RFIC.2015.7337717","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337717","url":null,"abstract":"This paper describes a technique in which a series inductance is used with a varactor to increase the varactor maximum to minimum capacitance ratio, thus enabling increased tuning range in an LC VCO. This technique is demonstrated through the implementation of an LC VCO tunable over a range greater than an octave, specifically 10.5 to 24 GHz (78%). The VCO is implemented within a fractional-N synthesizer in 32nm SOI CMOS to achieve continuous tuning from a fixed reference and achieves -128 to -119 dBc/Hz phase noise at 10MHz offset from the carrier across the tuning range. Output divider circuits are used to obtain all frequencies down to 660MHz.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121641007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 17.8 dBm 110–130 GHz Power Amplifier and doubler chain in SiGe BiCMOS technology 采用SiGe BiCMOS技术的17.8 dBm 110-130 GHz功率放大器和倍频链
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337787
R. Ben Yishay, D. Elad
{"title":"A 17.8 dBm 110–130 GHz Power Amplifier and doubler chain in SiGe BiCMOS technology","authors":"R. Ben Yishay, D. Elad","doi":"10.1109/RFIC.2015.7337787","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337787","url":null,"abstract":"A D-Band ×2 frequency multiplier-amplifier chain implemented in a fT/fMAX = 250/330 GHz 0.12 μm SiGe BiCMOS technology is presented. The chain achieves a peak output power of 17.8 dBm at 115 GHz and consists of input balun and push-push frequency doubler which drives a balanced three stages Power Amplifier (PA). It operates from 110 GHz to 130 GHz (3 dB power bandwidth) with -2 dBm input power at V-Band and consumes a total DC power of 600 mW. The PA achieves output 1 dB compression point and saturated power of 13.5 and 17.6 dBm, respectively, at 120 GHz and peak small signal gain of 32 dB.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122485059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A Sub-GHz low-power transceiver with PAPR-tolerant power amplifier for 802.11ah applications 一款Sub-GHz低功耗收发器，具有抗papr功率放大器，适用于802.11ah应用
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337747
Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Zhihua Wang, Yichuang Sun, B. Chi
{"title":"A Sub-GHz low-power transceiver with PAPR-tolerant power amplifier for 802.11ah applications","authors":"Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Zhihua Wang, Yichuang Sun, B. Chi","doi":"10.1109/RFIC.2015.7337747","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337747","url":null,"abstract":"A fully-integrated Sub-GHz low-power transceiver (TRX) for 802.11ah applications is presented. The receiver takes both advantages of Low-IF/Zero-IF architectures while supporting 1/2/8MHz reconfigurable signal bandwidth. A Σ-Δ fractional-N PLL with Class-C VCO is employed to provide the LOs. In order to enhance the power amplifier (PA) back-off efficiency, a Peak-to-Average-Power-Ratio (PAPR) tolerant technique is proposed with the aid of a power control loop to dynamically detect the input signal PAPR and flexibly reconfigures the PA's operation modes. With digitally-assisted self-calibrations for LO leakage and image rejection, the transmitter obtains -51.6dBc LO leakage and 51.2dBc image rejection ratio (IRR). A JESD207 interface is also included to communicate with the digital baseband. Implemented in 180nm CMOS, the receiver achieves 4dB NF and dissipates 18.9mW from a 1.7V supply. The CMOS PA achieves 13.6dBm output P1dB with 25.5% PAE in high power mode (HPM) and ×2.61 PAE improvement at 7dB back-off power in low power mode (LPM).","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130557899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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