{"title":"A 6.39GHz–14GHz series resonator mode-switching oscillator with 186–188dB FoM and 197dB FoMA in 65nm CMOS","authors":"Abhishek Agrawal, A. Natarajan","doi":"10.1109/RFIC.2015.7337739","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337739","url":null,"abstract":"CMOS LC voltage-controlled oscillators (VCO) with octave frequency tuning-range (FTR) are attractive for wideband radios. An area and power-efficient resonant mode-switching approach is presented that enables wide-FTR oscillators without compromising inductor Q, resulting in low phase noise and high VCO Figure-of-Merit (FoM). The proposed series resonator mode-switching approach results in a 6.4GHz to 14GHz VCO (74.6% FTR) in 65nm CMOS that achieves 186dB-188dB FoM. The scalability of this approach towards achieving even larger FTR is also demonstrated by a triple-mode 2.2GHz to 8.7GHz (119% FTR) VCO.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130709947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Chung, Po-Yu Chang, Meng-Hsiung Hung, Ming-Yeh Hsu, Che-Hung Liao, Chun-Wei Lin
{"title":"Dual-band integrated Wi-Fi PAs with load-line adjustment and phase compensated power detector","authors":"Y. Chung, Po-Yu Chang, Meng-Hsiung Hung, Ming-Yeh Hsu, Che-Hung Liao, Chun-Wei Lin","doi":"10.1109/RFIC.2015.7337745","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337745","url":null,"abstract":"A load-line adjusted 2.4GHz PA is designed to operate in full power (18dBm/150mA) & mid power (7dBm/19mA) in OFDM with ~130mA saving. To improve network throughput in dense environment with per-packet TX power control, the phase-compensated power detector achieves ±0.6dB accuracy for the entire 5GHz band over 2:1 VSWR and 16dBm±0.25dB over channel flatness in VHT80MCS9. The chip area is 0.21mm2 for load-line adjusted 2.4GHz PA and 0.13 mm2 for 5GHz PA with power detector.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115688479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wen Yuan, V. Aparin, J. Dunworth, L. Seward, J. Walling
{"title":"A quadrature switched capacitor power amplifier in 65nm CMOS","authors":"Wen Yuan, V. Aparin, J. Dunworth, L. Seward, J. Walling","doi":"10.1109/RFIC.2015.7337723","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337723","url":null,"abstract":"This paper presents a quadrature switched-capacitor power amplifier (SCPA) that achieves similar output power and efficiency as polar/EER based digital PAs. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array in the charge domain. The SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. This counteracts losses associated with the signal combination. Unlike polar/EER counterparts, the quadrature SCPA requires no wideband phase modulator or delay matching circuitry. The SCPA delivers a peak output power of 20.5 dBm with a peak PAE of 20%.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122972889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 3.6cm2 wirelessly-powered UWB SoC with −30.7dBm rectifier sensitivity and sub-10cm range resolution","authors":"Jian Kang, P. Chiang, A. Natarajan","doi":"10.1109/RFIC.2015.7337753","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337753","url":null,"abstract":"This paper discusses the design of a battery-less wirelessly-powered UWB system-on-a-chip (SoC) tag for area-constrained localization applications. An antenna-rectifier co-design methodology optimizes sensitivity and increases range under tag area constraints. A low-voltage (0.8-V) UWB TX enables high rectifier sensitivity by reducing required rectifier output voltage. The 2.4GHz rectifier, power-management unit and 8GHz UWB TX are integrated in 65nm CMOS and the rectifier demonstrates state-of-the-art -30.7dBm sensitivity for 1V output with only 1.3cm2 antenna area, representing a 2.3× improvement in sensitivity over previously published work, at 2.6× higher frequency with 9× smaller antenna area. Measurements in an office corridor demonstrate 20m range with 36dBm TX EIRP. The 0.8-V 8GHz UWB TX consumes 64pJ/pulse at 28MHz pulse repetition rate and achieves 2.4GHz -10dB bandwidth. Wireless measurements demonstrate sub-10cm range resolution at range > 10m.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124722544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digitally intensive transmitter employing RF pulse width modulation for IoT applications","authors":"Hyejeong Song, R. Gharpurey","doi":"10.1109/RFIC.2015.7337727","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337727","url":null,"abstract":"A CMOS RF-PWM transmitter with a Class-D power amplifier (PA) is proposed for Internet of Things (IoT) applications. The transmitter utilizes two PLL-based PWM generators to convert baseband signals into an RF-PWM signal without an upconverter. For an LTE signal with a 1.4 MHz bandwidth and a 6.4 dB peak-to-average ratio (PAR), the RF-PWM transmitter achieves a power-added efficiency (PAE) of 17.5%, an error vector magnitude (EVM) of -24.9 dB, and an adjacent channel leakage ratio (ACLR) of -31 dBc at an average output power of 16.1 dBm. The transmitter achieves a peak output power of 22.4 dBm with 46.6% PAE, and 38.8% efficiency for the full RF-PWM transmitter including PAs.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124930865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sub-harmonic wireless injection locking of a THz CMOS chip array","authors":"S. Jameson, E. Halpern, E. Socher","doi":"10.1109/RFIC.2015.7337718","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337718","url":null,"abstract":"A novel concept is introduced for generating high power frequency locked THz radiating based on CMOS chips. The concept is based on an array of CMOS VCO chips with on-chip ring antennas. With fundamental mm-wave oscillation around 115 GHz, the 3rd harmonic of 0.35 THz is radiated with record total radiated power (TRP) of -4.3 dBm, EIRP of +3.8 dBm, DC-to-THz efficiency of 1.4% and phase noise better than -95 dBc/Hz at 10 MHz offset. Using a buffer-less Colpitts topology both improves the output power and efficiency but also allows wireless locking of the VCO fundamental frequency using the on-chip antenna, which is an RF-choke for that frequency. This allows wireless coupling between array CMOS chip elements integrated on-board for mutual locking and also wireless locking to an external D-band reference. The concept is demonstrated using a 1×4 array of CMOS radiating chips. The sources can be tuned from 343 to 347 GHz and the injection locking range is around 80 MHz. The 1×4 array has an EIRP of +13.8 dBm, a TRP and DC-to-THz efficiency of +1 dBm and 1.2%, respectively. The 1×4 array locked signal follows the phase noise of the external reference (+9.5 dB) up to a locking range around 80 MHz. This new concept enables simple and cost effective locked CMOS THz scalable source arrays.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121991768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Barbe, L. Lucci, A. Siligaris, P. Vincent, O. Faynot
{"title":"4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors","authors":"J. Barbe, L. Lucci, A. Siligaris, P. Vincent, O. Faynot","doi":"10.1109/RFIC.2015.7337778","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337778","url":null,"abstract":"RF small-signal performances of Ultra-Thin Body and Box FDSOI transistors are evaluated using state-of-the-art 4-port characterization in the 100MHz-24GHz frequency range. Front-Gate cut-off frequencies and related figures of merit are extracted to assess the capabilities of the technology at 28 nm technology node for RF applications. Back-Gate cut-off frequency is also extracted and shown to be in the 80GHz range, while front-gate cut-off is higher than 380GHz. A 4-port S-parameter RF extraction for a SPICE model featuring gate width scalability is described.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127689193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Joseph Cali, C. Grens, S. E. Turner, D. Jansen, L. Kushner
{"title":"20-GHz PLL-based configurable frequency generator in 180nm SiGe-on-SOI BiCMOS","authors":"Joseph Cali, C. Grens, S. E. Turner, D. Jansen, L. Kushner","doi":"10.1109/RFIC.2015.7337790","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337790","url":null,"abstract":"This paper presents a configurable frequency generator (CFG) capable of synthesizing frequencies between 10 MHz and 20 GHz with superior far-out phase noise of less than -150 dBc/Hz at 100 MHz offset when synthesizing >10 GHz, reference spurs less than -70 dBc, settling times of less 3 μs, and support for multiple reference frequencies through the use of a programmable bandwidth on-chip loop filter. The CFG is implemented in a 180nm SiGe-on-SOI BiCMOS process that enables high-frequency oscillation in the voltage-controlled oscillator (VCO), low parasitic switches for programmable passives, low phase noise HBTs, and excellent isolation between components sharing the same substrate.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130843764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 38 GHz inverse class-F power amplifier with 38.5% peak PAE, 16.5 dB gain, and 50 mW Psat in 0.13-µm SiGe BiCMOS","authors":"S. Y. Mortazavi, Kwang-Jin Koh","doi":"10.1109/RFIC.2015.7337742","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337742","url":null,"abstract":"This paper presents a 38 GHz 2-stage harmonic-tuned power amplifier consisted of a class-F<sup>-1</sup> output power amplifier proceeded by a class-AB driving stage in 0.13 μm SiGe BiCMOS technology. In order to shape highly efficient class-F<sup>-1</sup> current and voltage waveforms, the PA adopts multi-resonance series and parallel load networks that modulate load impedance to generate an optimum 50-Ω for signal band, high impedance at the 2<sup>nd</sup> harmonic band and low impedance at the 3<sup>rd</sup> harmonic band. Inter-stage matching between the driver and output stage is also applied to deliver optimal power to the output stage with a maximum PAE, resulting in 38.5% of peak PAE with 50 mW P<sub>sat</sub> at 38 GHz, which is one of the highest PAEs in silicon technology at mm-wave. The chip size is 0.9×0.55 μm<sup>2</sup> including all pads.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125794127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"InP HBT/GaN HEMT/Si CMOS heterogeneous integrated Q-band VCO-amplifier chain","authors":"Yi-Cheng Wu, Monte K. Watanabe, T. LaRocca","doi":"10.1109/RFIC.2015.7337699","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337699","url":null,"abstract":"A Q-band DAHI (Diverse Accessible Heterogeneous Integration) multi-technology VCO-amplifier chain is presented. The DAHI integration process is composed of InP HBT, GaN HEMT and 65nm CMOS. The InP VCO demonstrated 2GHz of tuning range at 35GHz while the GaN amplifier provides 15dB gain.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127746365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}