{"title":"一个38 GHz反f类功率放大器，峰值PAE为38.5%，增益为16.5 dB, Psat为50 mW，采用0.13-µm SiGe BiCMOS","authors":"S. Y. Mortazavi, Kwang-Jin Koh","doi":"10.1109/RFIC.2015.7337742","DOIUrl":null,"url":null,"abstract":"This paper presents a 38 GHz 2-stage harmonic-tuned power amplifier consisted of a class-F<sup>-1</sup> output power amplifier proceeded by a class-AB driving stage in 0.13 μm SiGe BiCMOS technology. In order to shape highly efficient class-F<sup>-1</sup> current and voltage waveforms, the PA adopts multi-resonance series and parallel load networks that modulate load impedance to generate an optimum 50-Ω for signal band, high impedance at the 2<sup>nd</sup> harmonic band and low impedance at the 3<sup>rd</sup> harmonic band. Inter-stage matching between the driver and output stage is also applied to deliver optimal power to the output stage with a maximum PAE, resulting in 38.5% of peak PAE with 50 mW P<sub>sat</sub> at 38 GHz, which is one of the highest PAEs in silicon technology at mm-wave. The chip size is 0.9×0.55 μm<sup>2</sup> including all pads.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A 38 GHz inverse class-F power amplifier with 38.5% peak PAE, 16.5 dB gain, and 50 mW Psat in 0.13-µm SiGe BiCMOS\",\"authors\":\"S. Y. Mortazavi, Kwang-Jin Koh\",\"doi\":\"10.1109/RFIC.2015.7337742\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 38 GHz 2-stage harmonic-tuned power amplifier consisted of a class-F<sup>-1</sup> output power amplifier proceeded by a class-AB driving stage in 0.13 μm SiGe BiCMOS technology. In order to shape highly efficient class-F<sup>-1</sup> current and voltage waveforms, the PA adopts multi-resonance series and parallel load networks that modulate load impedance to generate an optimum 50-Ω for signal band, high impedance at the 2<sup>nd</sup> harmonic band and low impedance at the 3<sup>rd</sup> harmonic band. Inter-stage matching between the driver and output stage is also applied to deliver optimal power to the output stage with a maximum PAE, resulting in 38.5% of peak PAE with 50 mW P<sub>sat</sub> at 38 GHz, which is one of the highest PAEs in silicon technology at mm-wave. The chip size is 0.9×0.55 μm<sup>2</sup> including all pads.\",\"PeriodicalId\":121490,\"journal\":{\"name\":\"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2015.7337742\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2015.7337742","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 38 GHz inverse class-F power amplifier with 38.5% peak PAE, 16.5 dB gain, and 50 mW Psat in 0.13-µm SiGe BiCMOS
This paper presents a 38 GHz 2-stage harmonic-tuned power amplifier consisted of a class-F-1 output power amplifier proceeded by a class-AB driving stage in 0.13 μm SiGe BiCMOS technology. In order to shape highly efficient class-F-1 current and voltage waveforms, the PA adopts multi-resonance series and parallel load networks that modulate load impedance to generate an optimum 50-Ω for signal band, high impedance at the 2nd harmonic band and low impedance at the 3rd harmonic band. Inter-stage matching between the driver and output stage is also applied to deliver optimal power to the output stage with a maximum PAE, resulting in 38.5% of peak PAE with 50 mW Psat at 38 GHz, which is one of the highest PAEs in silicon technology at mm-wave. The chip size is 0.9×0.55 μm2 including all pads.
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