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Design methodology for controlled-Q resonators in OTA-based filters 基于ota的滤波器中可控q谐振器的设计方法
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-11-30 DOI: 10.1109/RFIC.2015.7337782
Saeed Ghamari, G. Tasselli, C. Botteron, P. Farine
{"title":"Design methodology for controlled-Q resonators in OTA-based filters","authors":"Saeed Ghamari, G. Tasselli, C. Botteron, P. Farine","doi":"10.1109/RFIC.2015.7337782","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337782","url":null,"abstract":"This paper presents a design methodology for high quality factor resonators based on operational transconductance amplifier (OTA) employed in active filters. The quality factor of a resonator, as its main specification, is translated to the requirements of the OTA. Moreover, the effects of the OTA's finite output resistance and internal poles are investigated. The results provide a useful chart and a simple methodology to design a resonator with a desired quality factor. The design methodology has been validated by fabricating a resonator with 8 MHz resonance frequency and a quality factor of around 10 using UMC 180-nm CMOS technology.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123934386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 30 Gb/s CMOS driver integrated with silicon photonics MZM 集成硅光子学MZM的30gb /s CMOS驱动器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-11-30 DOI: 10.1109/RFIC.2015.7337767
Ke Li, D. Thomson, Shenghao Liu, P. Wilson, G. Reed
{"title":"A 30 Gb/s CMOS driver integrated with silicon photonics MZM","authors":"Ke Li, D. Thomson, Shenghao Liu, P. Wilson, G. Reed","doi":"10.1109/RFIC.2015.7337767","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337767","url":null,"abstract":"A voltage mode modulator driver is proposed in the TSMC 65nm low power CMOS process. In the electrical testing, the driver itself can achieve a bit rate of 40Gb/s with the single-ended output swing of 1.65V. Unlike equivalent CML modulator drivers, when the proposed driver is integrated with the silicon photonic MZM, it does not require an additional biasing network. The integrated electro-optic transmitter can achieve 30Gb/s with an extinction ratio of 4.05dB, with the power consumption of main driver being 323mW.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132161647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
0.39–0.45THz symmetric MOS-varactor frequency tripler in 65-nm CMOS 0.39-0.45THz对称mos变容三倍频65纳米CMOS
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337758
Z. Ahmad, Insoo Kim, K. O. Kenneth
{"title":"0.39–0.45THz symmetric MOS-varactor frequency tripler in 65-nm CMOS","authors":"Z. Ahmad, Insoo Kim, K. O. Kenneth","doi":"10.1109/RFIC.2015.7337758","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337758","url":null,"abstract":"A broadband passive frequency tripler using an accumulation-mode symmetric MOS varactor (SVAR) in 65-nm bulk CMOS process is demonstrated. The measured output power (Pout) is >-15dBm over a 57GHz band. This tripler incorporating an on-chip patch antenna operates at frequencies between 390 and 456GHz, and achieves a peak Effective Isotropically Radiated Power (EIRP) of -5dBm. The measurement setup limited peak Pout and conversion loss is -3.2dBm and 15.2dB, respectively at 447GHz after antenna gain de-embedding. This is the highest reported output power for all CMOS sources operating above 350GHz and can be integrated with an on-chip input driver amplifier.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117143942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A wideband fractional-N synthesizer with low effort adaptive phase noise cancellation for low-power short-range standards 一种适用于低功率短距离标准的低功耗自适应相位噪声消除的宽带分数n合成器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337707
Ye Zhang, Jan Henning Mueller, B. Mohr, Lei Liao, A. Atac, R. Wunderlich, S. Heinen
{"title":"A wideband fractional-N synthesizer with low effort adaptive phase noise cancellation for low-power short-range standards","authors":"Ye Zhang, Jan Henning Mueller, B. Mohr, Lei Liao, A. Atac, R. Wunderlich, S. Heinen","doi":"10.1109/RFIC.2015.7337707","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337707","url":null,"abstract":"This paper presents a wideband low-spur fractional-N synthesizer with an adaptive noise cancellation technique. By adopting the classical loop filter, the ΣΔ quantization noise as well as the spurs are compensated with simple calibration circuits. The synthesizer is fully integrated in 130nm CMOS technology, consuming 0.33mm2 area and 8.3mW core power. It operates at 1.8 GHz carrier frequency with 1MHz bandwidth. The out-band phase noise is -129 dBc/Hz at 3MHz offset, the reference spur is -68 dBc, and the worst inband fractional spur is -56 dBc.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120857916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 55-GHz power-efficient frequency quadrupler with high harmonic rejection in 0.1-µm SiGe BiCMOS technology 采用0.1µm SiGe BiCMOS技术的55 ghz高效节能四倍频器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337756
Yi-Shin Yeh, B. Floyd
{"title":"A 55-GHz power-efficient frequency quadrupler with high harmonic rejection in 0.1-µm SiGe BiCMOS technology","authors":"Yi-Shin Yeh, B. Floyd","doi":"10.1109/RFIC.2015.7337756","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337756","url":null,"abstract":"This paper presents a V-band frequency quadrupler in 0.1-μm SiGe BiCMOS technology with 3-dB bandwidth from 44.8 to 57.2 GHz. The circuit employs cascode stacks comprising in-phase class-C common-emitter and anti-phase class-AB cascode devices to obtain current pulses at ×4 frequency. Four such cascodes driven with differential and tunable quadrature increase the 4th harmonic output power while suppressing all other harmonics 22 dB or more. Measurements show >7.4-dBm 4th harmonic output power, and >5.2% power efficiency for the core of the multiplier.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126852851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
RF performance of 28nm PolySiON and HKMG CMOS devices 28nm PolySiON和HKMG CMOS器件的射频性能
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337700
K. Chew, Aniket Agshikar, M. Wiatr, J. S. Wong, W. Chow, Zhihong Liu, T. Lee, Jinglin Shi, S. Lim, K. Sundaram, L. Chan, C. H. Cheng, N. Sassiat, Y. K. Yoo, A. Balijepalli, A. Kumta, C. Nguyen, R. Illgen, A. Mathew, C. Schippel, A. Romanescu, J. Watts, D. Harame
{"title":"RF performance of 28nm PolySiON and HKMG CMOS devices","authors":"K. Chew, Aniket Agshikar, M. Wiatr, J. S. Wong, W. Chow, Zhihong Liu, T. Lee, Jinglin Shi, S. Lim, K. Sundaram, L. Chan, C. H. Cheng, N. Sassiat, Y. K. Yoo, A. Balijepalli, A. Kumta, C. Nguyen, R. Illgen, A. Mathew, C. Schippel, A. Romanescu, J. Watts, D. Harame","doi":"10.1109/RFIC.2015.7337700","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337700","url":null,"abstract":"The impact of scaling in advanced RF/MS-CMOS has been extensively discussed but there has not been a publication that compares the RF characteristics of 28nm high-K metal gate HKMG and PolySiON technologies fabricated in the same facility. In this work, we show that HKMG improves transistor fT and increases varactor tunning range. However, it can actually decrease fmax. We examine how process features made to optimize cost and digital performance impact the RF performance. Process features which improve DC current and gm, including HKMG also give higher fT. However, fmax is sensitive to gate resistance and PolySiON has an advantage here.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115213492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 15-mW 7-GHz inductorless transimpedance amplifier and a 1-THz+ GBP limiting amplifier for 10GbE optical receivers 用于10GbE光接收器的15mw无电感跨阻放大器和1thz + GBP限制放大器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337795
S. Ray, M. Hella
{"title":"A 15-mW 7-GHz inductorless transimpedance amplifier and a 1-THz+ GBP limiting amplifier for 10GbE optical receivers","authors":"S. Ray, M. Hella","doi":"10.1109/RFIC.2015.7337795","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337795","url":null,"abstract":"An inductorless 10 Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier (LA) with third-order nested feedback is presented. The current-buffer based TIA employs an active Cherry-Hooper (CH) stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gbps operation in the presence of a 1pF photodiode input capacitance. The use of nested feedback in the four stage limiting amplifier enables a gain-bandwidth-product (GBP)>1THz without the use of area-consuming inductors. Implemented in IBM 130nm CMOS technology, the optical receiver achieves a BER<;10-12 at 10 Gbps for an input current of 30 μA, delivering 600 mV p-p at the output of the 50 Ω buffer. Optical testing confirmed a -13.8 dBm sensitivity for a data rate of 7.5 Gbps, mainly limited by the 850nm source used for measurement. The receiver dissipates 108mW from a 1.2V supply, while occupying a core area of only 0.08 mm2.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114560461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A dynamically-biased 2G/3G/4G multi-band transmitter with > 4dBm Pout, < −65dBc CIM3 and < −157dBc/Hz out-of-band noise in 28nm CMOS 一种动态偏置的2G/3G/4G多波段发射机，输出端为> 4dBm, CIM3 < - 65dBc，带外噪声< - 157dBc/Hz
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337726
S. Seth, Daehyun Kwon, S. Venugopalan, S. Son, Yongrong Zuo, V. Bhagavatula, Jae-Geol Lim, D. Oh, T. Cho
{"title":"A dynamically-biased 2G/3G/4G multi-band transmitter with > 4dBm Pout, < −65dBc CIM3 and < −157dBc/Hz out-of-band noise in 28nm CMOS","authors":"S. Seth, Daehyun Kwon, S. Venugopalan, S. Son, Yongrong Zuo, V. Bhagavatula, Jae-Geol Lim, D. Oh, T. Cho","doi":"10.1109/RFIC.2015.7337726","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337726","url":null,"abstract":"We present a highly-configurable, low-power, low-area, SAW-less TX architecture that is based on a dynamically-biased power mixer. All FDD/TDD bands for 4G LTE and 3G WCDMA/HSPA are supported in addition to 2G quad bands. The power-mixer bias current is dynamically adjusted based on the instantaneous baseband signal swing using a fully-differential hybrid full-wave rectifier / envelope detector circuit. Implemented in 28nm CMOS technology, the TX shows better than -157dBc/Hz RX-band noise emission and -41dBc ACLR for output powers up-to 4dBm across all 3G/4G bands. In addition, the TX can be configured to provide better than -65dBc CIM3, allowing it to meet stringent spurious emission specifications when transmitting 1RB 4G LTE signals in B13 / B26 / B1.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129786227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A highly integrated multiband LTE SiGe power amplifier for envelope tracking 用于包络跟踪的高集成多频带LTE SiGe功率放大器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337722
Yan Li, J. Ortiz, E. Spears
{"title":"A highly integrated multiband LTE SiGe power amplifier for envelope tracking","authors":"Yan Li, J. Ortiz, E. Spears","doi":"10.1109/RFIC.2015.7337722","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337722","url":null,"abstract":"This paper presents a highly integrated SiGe power amplifier (PA) for multiband long-term evolution (LTE). Two different harmonic loadings are investigated for the PA to achieve the optimized efficiencies for the envelope tracking (ET) and average power tracking (APT), respectively. By adopting the proper PA structure, our ET PA delivers >39% overall power-added efficiency (PAE) at the maximum output power (Pout) of 26.5 dBm with ACLREUTRA below -42 dB and EVM below 1% for the LTE QPSK 10 MHz at 699-716 MHz, 824-915 MHz and 1710-1980 MHz. At the back-off more than 5 dB below the maximum Pout, the ET PA is reconfigured to APT for remaining high overall PAE and linearity across a broad Pout range.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"21 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120899669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
0.4–6 GHz,17-dBm B1dB, 36-dBm IIP3 channel-selecting, low-noise amplifier for SAW-less 3G/4G FDD receivers 0.4-6 GHz, 17dbm B1dB, 36dbm IIP3选路，低噪声放大器，用于无saw 3G/4G FDD接收机
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337764
Cheng-kai Luo, P. Gudem, J. Buckwalter
{"title":"0.4–6 GHz,17-dBm B1dB, 36-dBm IIP3 channel-selecting, low-noise amplifier for SAW-less 3G/4G FDD receivers","authors":"Cheng-kai Luo, P. Gudem, J. Buckwalter","doi":"10.1109/RFIC.2015.7337764","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337764","url":null,"abstract":"A channel-selecting, low-noise amplifier (CSLNA) is presented that meets the requirements for a SAW-less diversity path receiver in frequency-division duplexing (FDD) cellular systems. An N-path filter is incorporated into the LNA feedback network to tune from 400 MHz to 6 GHz. The proposed CS-LNA creates close-in stopbands around the passband to suppress transmit (TX) blockers up to 17 dBm. This work reports an out-of-band (OOB) IIP3 of 36 dBm and IB IIP3 of 10 dBm with the maximum rejection larger than 60 dB. To the author's knowledge, this is the highest blocker rejection, power-handling capability and IIP3 for an LNA that is tunable over more than a decade.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116202851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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