Ye Zhang, Jan Henning Mueller, B. Mohr, Lei Liao, A. Atac, R. Wunderlich, S. Heinen
{"title":"一种适用于低功率短距离标准的低功耗自适应相位噪声消除的宽带分数n合成器","authors":"Ye Zhang, Jan Henning Mueller, B. Mohr, Lei Liao, A. Atac, R. Wunderlich, S. Heinen","doi":"10.1109/RFIC.2015.7337707","DOIUrl":null,"url":null,"abstract":"This paper presents a wideband low-spur fractional-N synthesizer with an adaptive noise cancellation technique. By adopting the classical loop filter, the ΣΔ quantization noise as well as the spurs are compensated with simple calibration circuits. The synthesizer is fully integrated in 130nm CMOS technology, consuming 0.33mm2 area and 8.3mW core power. It operates at 1.8 GHz carrier frequency with 1MHz bandwidth. The out-band phase noise is -129 dBc/Hz at 3MHz offset, the reference spur is -68 dBc, and the worst inband fractional spur is -56 dBc.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A wideband fractional-N synthesizer with low effort adaptive phase noise cancellation for low-power short-range standards\",\"authors\":\"Ye Zhang, Jan Henning Mueller, B. Mohr, Lei Liao, A. Atac, R. Wunderlich, S. Heinen\",\"doi\":\"10.1109/RFIC.2015.7337707\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a wideband low-spur fractional-N synthesizer with an adaptive noise cancellation technique. By adopting the classical loop filter, the ΣΔ quantization noise as well as the spurs are compensated with simple calibration circuits. The synthesizer is fully integrated in 130nm CMOS technology, consuming 0.33mm2 area and 8.3mW core power. It operates at 1.8 GHz carrier frequency with 1MHz bandwidth. The out-band phase noise is -129 dBc/Hz at 3MHz offset, the reference spur is -68 dBc, and the worst inband fractional spur is -56 dBc.\",\"PeriodicalId\":121490,\"journal\":{\"name\":\"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"14 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2015.7337707\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2015.7337707","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A wideband fractional-N synthesizer with low effort adaptive phase noise cancellation for low-power short-range standards
This paper presents a wideband low-spur fractional-N synthesizer with an adaptive noise cancellation technique. By adopting the classical loop filter, the ΣΔ quantization noise as well as the spurs are compensated with simple calibration circuits. The synthesizer is fully integrated in 130nm CMOS technology, consuming 0.33mm2 area and 8.3mW core power. It operates at 1.8 GHz carrier frequency with 1MHz bandwidth. The out-band phase noise is -129 dBc/Hz at 3MHz offset, the reference spur is -68 dBc, and the worst inband fractional spur is -56 dBc.