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2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A 0.5V 0.5mW switching current source oscillator 一个0.5V 0.5mW开关电流源振荡器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337735
M. Babaie, M. Shahmohammadi, R. Staszewski
{"title":"A 0.5V 0.5mW switching current source oscillator","authors":"M. Babaie, M. Shahmohammadi, R. Staszewski","doi":"10.1109/RFIC.2015.7337735","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337735","url":null,"abstract":"This paper proposes a new RF oscillator topology that is suitable for ultra-low voltage and power applications. By employing alternating current source transistors, the structure combines the benefits of low supply voltage operation of conventional NMOS cross-coupled oscillators together with high current efficiency of the complementary push-pull oscillators. In addition, the 1/f noise upconversion is also reduced. The 40nm CMOS prototype exhibits an average FoM of 189.5 dBc/Hz over 4-5 GHz tuning range, dissipating 0.5mW from 0.5V power supply, while abiding by the technology manufacturing rules.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"34 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116493331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 24 GS/s single-core flash ADC with 3 bit resolution in 28 nm low-power digital CMOS 24gs /s 3位分辨率的单核闪存ADC，采用28nm低功耗数字CMOS
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337776
G. Tretter, M. Khafaji, D. Fritsche, C. Carta, F. Ellinger
{"title":"A 24 GS/s single-core flash ADC with 3 bit resolution in 28 nm low-power digital CMOS","authors":"G. Tretter, M. Khafaji, D. Fritsche, C. Carta, F. Ellinger","doi":"10.1109/RFIC.2015.7337776","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337776","url":null,"abstract":"This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit (FOM) of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128012804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A vertical solenoid inductor for noise coupling minimization in 3D-IC 用于3D-IC中噪声耦合最小化的垂直螺线管电感
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337703
G. Yahalom, Alice Wang, U. Ko, A. Chandrakasan
{"title":"A vertical solenoid inductor for noise coupling minimization in 3D-IC","authors":"G. Yahalom, Alice Wang, U. Ko, A. Chandrakasan","doi":"10.1109/RFIC.2015.7337703","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337703","url":null,"abstract":"This paper presents the use of an integrated solenoid inductor in three dimensional integrated circuits (3D-IC) for improved noise mitigation. The structure is fabricated in a two-tier, stacked 28nm CMOS using through silicon vias (TSV). The structure is implemented as part of an LC voltage-controlled oscillator (VCO), and exhibits 6dB improvement in phase noise and 14dB less coupling from adjacent digital clock lines compared to a planar two-turn inductor.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134256158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An impedance sensor for MEMS adaptive antenna matching 一种用于MEMS自适应天线匹配的阻抗传感器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337784
Armin Tavakol, R. Staszewski
{"title":"An impedance sensor for MEMS adaptive antenna matching","authors":"Armin Tavakol, R. Staszewski","doi":"10.1109/RFIC.2015.7337784","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337784","url":null,"abstract":"We propose a new calibration mechanism for passive adaptive cellular antenna matching network containing MEMS-based tunable devices. To avoid expensive and bulky couplers and reference circuitry, the tuner contains voltage and current sensors inserted before the antenna matching network. The sensed complex impedance generates 2-bit update controls for the tuning algorithm, which drives the MEMS-based tunable devices. The impedance sensing IC is designed to operate in the frequency range of 1.7-2.7 GHz and the clock frequency is 50 kHz.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131506307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Dual-vector phase rotator for Doherty beamformers Doherty波束形成器的双矢量相位旋转器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337772
Kevin Greene, B. Floyd
{"title":"Dual-vector phase rotator for Doherty beamformers","authors":"Kevin Greene, B. Floyd","doi":"10.1109/RFIC.2015.7337772","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337772","url":null,"abstract":"A 28-GHz dual-vector phase rotator is introduced, having the capability of generating two quadrature output signals that track one another in phase. The 4-bit dual-vector rotator was implemented in IBM 0.12-μm SiGe BiCMOS technology and achieves full 360o phase shifting, RMS phase and amplitude errors of <; 5 degrees and <; 0.8 dB, respectively for both output vectors, and 10-12 dB of gain. Output 1-dB compression points for both quadrature outputs is -6.5 to -4.4 dBm, suitable for directly driving a Doherty amplifier in a 28-GHz beamformer.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131022767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Rel-12 2G/3G/LTE-advanced 3CC receiver 一个Rel-12 2G/3G/LTE-advanced 3CC接收器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337725
M. Mikhemar, M. Kahrizi, J. Leete, B. Pregardier, N. Vakilian, A. Hadji-Abdolhamid, M. Vadipour, P. Ye, J. Chiu, B. Saeidi, G. Theodoratos, M. Nariman, Y. Chang, F. Etemadi, B. Nourani, A. Tarighat, P. Mudge, Z. Zhou, N. Liu, C. Guan, K. Juan, B. Zhao, R. Magoon, M. Rofougaran, R. Rofougaran
{"title":"A Rel-12 2G/3G/LTE-advanced 3CC receiver","authors":"M. Mikhemar, M. Kahrizi, J. Leete, B. Pregardier, N. Vakilian, A. Hadji-Abdolhamid, M. Vadipour, P. Ye, J. Chiu, B. Saeidi, G. Theodoratos, M. Nariman, Y. Chang, F. Etemadi, B. Nourani, A. Tarighat, P. Mudge, Z. Zhou, N. Liu, C. Guan, K. Juan, B. Zhao, R. Magoon, M. Rofougaran, R. Rofougaran","doi":"10.1109/RFIC.2015.7337725","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337725","url":null,"abstract":"This work presents a cellular receiver capable of receiving three simultaneous channels with an aggregate bandwidth of 60 MHz, enabling a 300 Mbps downlink rate. The receiver has 16 RF LNA ports covering the cellular bands within the 572-2700 MHz frequency range. It supports LTE-advanced Rel-12 Cat6, HSPA+ Rel-11, TD-SCDMA Rel-9, and GSM/EDGE Rel-9. The 40 nm CMOS receiver consumes 13.7 mA and 17.6 mA of battery current in 3G and LTE modes, respectively, including the PLL, DCXO, and bia sing for a single channel.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133683694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 60 GHz same-channel full-duplex CMOS transceiver and link based on reconfigurable polarization-based antenna cancellation 基于可重构极化天线对消的60 GHz同通道全双工CMOS收发器和链路
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337697
T. Dinc, A. Chakrabarti, H. Krishnaswamy
{"title":"A 60 GHz same-channel full-duplex CMOS transceiver and link based on reconfigurable polarization-based antenna cancellation","authors":"T. Dinc, A. Chakrabarti, H. Krishnaswamy","doi":"10.1109/RFIC.2015.7337697","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337697","url":null,"abstract":"This paper describes a direct-conversion 45nm SOI CMOS 60 GHz transceiver for same-channel full duplex applications. A novel polarization-based wideband self-interference cancellation (SIC) technique in the antenna domain is described that can be reconfigured from the IC. In order to achieve the high levels of required SIC, a second RF cancellation path from the transmitter output to the LNA output with >30 dB gain control and >360° phase control is also integrated. The TX and RX share the same LO to reduce the impact of phase noise on SIC. Antenna and RF cancellation together enable >70 dB of total self-interference suppression even in the presence of nearby reflectors. In conjuction with digital SIC impemented in MATLAB, a same-channel full-duplex link is demonstrated over 0.7 m. To the best of our knowledge, this work demonstrates the first fully-integrated full-duplex transceiver front-end and mm-wave link. While not our focus, the transceiver also achieves state-of-the-art saturated output power of +15 dBm, peak TX efficiency of 15.3% and RX NF of 4 dB.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124585955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 2×2 Dynamic Polarization-Controlling integrated phased array 2×2动态极化控制集成相控阵
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337744
A. Safaripour, S. Bowers, K. Dasgupta, A. Hajimiri
{"title":"A 2×2 Dynamic Polarization-Controlling integrated phased array","authors":"A. Safaripour, S. Bowers, K. Dasgupta, A. Hajimiri","doi":"10.1109/RFIC.2015.7337744","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337744","url":null,"abstract":"Radiator arrays with Dynamic Polarization Control (DPC) and 2D beam steering enable polarization matching to the receiver antenna regardless of its polarization, orientation, and location. A fully integrated 122.9 GHz 2×2 DPC multi-port driven phased array radiates all linear polarizations (0°-180° polarization angles) with axial ratios above 14 dB, and controls the axial ratio from 1.2 dB (circular) to 17.8 dB (linear) with a maximum EIRP of +12.3 dBm and 2D beam steering of up to 15°.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114517502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Digital pulse-width pulse-position modulator in 28 nm CMOS for carrier frequencies up to 1 GHz 数字脉宽脉位调制器在28纳米CMOS载波频率高达1ghz
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337714
J. Digel, M. Grozing, Martin Schmidt, M. Berroth, C. Haslach
{"title":"Digital pulse-width pulse-position modulator in 28 nm CMOS for carrier frequencies up to 1 GHz","authors":"J. Digel, M. Grozing, Martin Schmidt, M. Berroth, C. Haslach","doi":"10.1109/RFIC.2015.7337714","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337714","url":null,"abstract":"A fully digital pulse-width pulse-position modulator (D-PWPM) is proposed that is capable of providing pulse sequences for a switching-mode power amplifier. The pulse sequences are generated according to 6-bit digital input words defining the positions of the rising and falling edges without the need for tunable analog delay cells. All possible edge positions are derived by division and phase interpolation of a digital input clock signal that is a multiple of the carrier frequency. CMOS selectors provide two signals which carry the actual rising and falling edge positions to special symmetric CMOS NOR and NAND gates. They finally generate the modulated pulse sequence. The D-PWPM is fabricated in a 28 nm low-power CMOS technology and the circuit core dissipates 53mW from a 1 V supply. Sinusoidal double-sideband suppressed-carrier modulation of a 1 GHz carrier demonstrates the capability of the D-PWPM to operate as an RF bandpass mode DAC. With a carrier frequency of 983.04MHz, an SFDR of 45.6 dB is achieved for a low-frequency modulation and 33.4 dB near Nyquist frequency. Data transmission at 491.52MBit/s is demonstrated with a 16-QAM.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123452118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Compact 160-GHz amplifier with 15-dB peak gain and 41-GHz 3-dB bandwidth 紧凑型160ghz放大器，15db峰值增益和41ghz 3db带宽
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337691
S. Hara, K. Katayama, K. Takano, I. Watanabe, N. Sekine, A. Kasamatsu, T. Yoshida, S. Amakawa, M. Fujishima
{"title":"Compact 160-GHz amplifier with 15-dB peak gain and 41-GHz 3-dB bandwidth","authors":"S. Hara, K. Katayama, K. Takano, I. Watanabe, N. Sekine, A. Kasamatsu, T. Yoshida, S. Amakawa, M. Fujishima","doi":"10.1109/RFIC.2015.7337691","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337691","url":null,"abstract":"This paper presents a compact wideband amplifier at 160 GHz in 40-nm CMOS. Typical wideband amplifier design requires higher-order matching networks and more gain stages, both of which demand larger die area. The presented 8-stage amplifier uses a compact “fishbone” layout technique, and its core size is as small as 190 × 123 μm2. A small-signal gain of 15 dB at 160 GHz and a 3-dB bandwidth of 41 GHz are achieved. It consumes 117 mW from a 0.9 V voltage supply.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129526528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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