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An IF 8-element 2-beam bit-stream band-pass beamformer 中频8元2波束位流带通波束形成器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337761
J. Jeong, Nicholas Collins, M. Flynn
{"title":"An IF 8-element 2-beam bit-stream band-pass beamformer","authors":"J. Jeong, Nicholas Collins, M. Flynn","doi":"10.1109/RFIC.2015.7337761","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337761","url":null,"abstract":"We introduce a new ADC-digital co-design approach to IF digital beamforming (DBF) that combines continuous-time band-pass ΔΣ modulators (CTBPDSMs) and bit-stream processing (BSP) to achieve highly flexible and low-cost DBF. Our prototype DBF IC digitizes eight 260MHz IF signals at 1040MS/s with band-pass ADCs, and performs DBF directly on the over-sampled, un-decimated ADC outputs, achieving band-pass filtering in both spatial and frequency domains. With 12b programmable complex weights, the prototype generates two simultaneous beams, and achieves an SNDR of 63.3dB with an 8.9dB array improvement over a 10MHz bandwidth. Fabricated in 65nm CMOS, the prototype is the first IC implementation of IF DBF, occupies 0.28mm2, and consumes 124mW.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"76 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129353935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 192MHz differential XO based frequency quadrupler with sub-picosecond jitter in 28nm CMOS 基于192MHz差分XO的频率四倍器，具有亚皮秒抖动，28nm CMOS
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337704
M. Ghahramani, Yashar Rajavi, Alireza Khalili, A. Kavousian, Beomsup Kim, M. Flynn
{"title":"A 192MHz differential XO based frequency quadrupler with sub-picosecond jitter in 28nm CMOS","authors":"M. Ghahramani, Yashar Rajavi, Alireza Khalili, A. Kavousian, Beomsup Kim, M. Flynn","doi":"10.1109/RFIC.2015.7337704","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337704","url":null,"abstract":"A low jitter 192MHz crystal reference quadrupler leverages a new active inductor based 48MHz differential XO, two skewed inverters, a new duty cycle correction circuit, and a frequency doubler. The 192MHz quadrupler can serve as a fast, low jitter reference for a low phase noise PLL and requires far less power and area than reference multiplying PLL or MDLL circuits. The measured RMS jitter is 168fs for the XO, and 184fs for 96MHz output (192MHz divide by 2). The entire circuit, including the XO, draws 5.5mA from a 1V supply and occupies 0.045mm2. To our best knowledge, this is the first reference frequency quadrupler with sub-picosecond jitter.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130575015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 54.4-mW 4th-order quadrature bandpass CT ΣΔ modulator with 33-MHz BW and 10-bit ENOB for a GNSS receiver 用于GNSS接收机的54.4 mw四阶正交带通CT ΣΔ调制器，BW为33mhz, ENOB为10位
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337775
Junfeng Zhang, Zehong Zhang, Yang Xu, Yichuang Sun, B. Chi
{"title":"A 54.4-mW 4th-order quadrature bandpass CT ΣΔ modulator with 33-MHz BW and 10-bit ENOB for a GNSS receiver","authors":"Junfeng Zhang, Zehong Zhang, Yang Xu, Yichuang Sun, B. Chi","doi":"10.1109/RFIC.2015.7337775","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337775","url":null,"abstract":"A 4th-order quadrature bandpass continuous-time sigma-delta modulator for a GNSS receiver is presented. With significantly wide bandwidth, the modulator is able to digitalize the down-conversed GNSS signals in two adjacent signal bands simultaneously. This makes it possible to realize simultaneous dual-frequency reception from two satellite systems with one receiver channel instead of two independent channels. A direct RZ feedback is introduced into the input of the last integrator to realize ELD compensation. Power-efficient amplifiers are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-bit quantizers. Implemented in 180nm CMOS, the modulator achieves 62.1dB peak SNDR, 64dB DR and 59.3dB image rejection ratio (IRR), and consumes 54.4mW from a 1.8V power supply.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127877921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A positive feedback passive mixer-first receiver front-end 一个正反馈无源混频器优先接收器前端
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337709
Anders Nejdel, Mohammed Abdulaziz, M. Tormanen, H. Sjoland
{"title":"A positive feedback passive mixer-first receiver front-end","authors":"Anders Nejdel, Mohammed Abdulaziz, M. Tormanen, H. Sjoland","doi":"10.1109/RFIC.2015.7337709","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337709","url":null,"abstract":"This paper presents a technique to reduce the noise figure of a passive mixer-first receiver front-end. By using lower than 50Ω switch resistance in the current-mode passive mixer and introducing a positive feedback from baseband to the RF-input, it can be well matched close to fLO while achieving a noise figure below 3dB, which is otherwise a fundamental limit. A quadrature front-end prototype for a direct conversion receiver has been implemented in 65nm CMOS, occupying an active area of 0.23mm2 with a frequency operation ranging from 0.7 to 3.8 GHz. The prototype achieves a minimum noise figure of 2.5dB, an out-of-band 1dB compression point of +3dBm, with IIP3 and IIP2 exceeding +26 and +65dBm, respectively. The current consumption from a 1.2V supply is between 22.8 and 62.8mA, depending on frequency operation.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"116 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126392439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A wideband under-sampling blocker detector with a 0.7–2.7 GHz mixer-first receiver 一种带0.7-2.7 GHz混频器优先接收器的宽带欠采样阻塞检测器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337773
O. Viitala, M. Kaltiokallio, M. Kosunen, K. Stadius, J. Ryynanen
{"title":"A wideband under-sampling blocker detector with a 0.7–2.7 GHz mixer-first receiver","authors":"O. Viitala, M. Kaltiokallio, M. Kosunen, K. Stadius, J. Ryynanen","doi":"10.1109/RFIC.2015.7337773","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337773","url":null,"abstract":"This paper presents a low power wideband blocker detector consisting of an under-sampling SAR ADC connected to the RF input node of a wideband mixer-first receiver. The original carrier frequency of the blocker is determined from folded spectra by using three FFTs sampled at different rates whose ratios correspond to prime numbers. The detector is targeted for blocker power levels between 0 and -30 dBm within frequency range of 0.7-2.7 GHz. The achieved ADC maximum SNDR of 28 dB, together with 10 dB input buffer gain control, provide sufficient blocker detection sensitivity in the desired range. The measured sampled input signal spectra show the designed circuits capability to simultaneously detect narrowband and wideband blockers. The reconstructed folded spectrum shows the original blocker frequencies. The power consumption of the wideband detector is only 7 mW, while the receiver consumes 42 mW.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"532 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123452805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Auto-calibrating threshold compensation technique for RF energy harvesters 射频能量采集器的自校准阈值补偿技术
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337734
K. Gharehbaghi, O. Zorlu, F. Koçer, H. Kulah
{"title":"Auto-calibrating threshold compensation technique for RF energy harvesters","authors":"K. Gharehbaghi, O. Zorlu, F. Koçer, H. Kulah","doi":"10.1109/RFIC.2015.7337734","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337734","url":null,"abstract":"This paper presents the design of a new threshold compensation technique for UHF Dickson rectifiers. The proposed solution addresses the efficiency reduction of previous architectures especially under large input powers. The measurements show that the proposed technique achieves very good efficiency within 10 dBm variation of the input power. Therefore, the technique is suitable for applications where the incident power is not constant. Thanks to the reduction in the reverse leakage current, a peak efficiency of 34% at 433 MHz was measured.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 312GHz antenna array receiver in 65nm CMOS utilizing self-oscillating 3X subharmonic mixer frontend 采用自振荡3X次谐波混频器前端的65nm CMOS 312GHz天线阵列接收器
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337694
Yen-Ju Chen, Ta-Shun Chu
{"title":"A 312GHz antenna array receiver in 65nm CMOS utilizing self-oscillating 3X subharmonic mixer frontend","authors":"Yen-Ju Chen, Ta-Shun Chu","doi":"10.1109/RFIC.2015.7337694","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337694","url":null,"abstract":"A 312GHz antenna array receiver is presented in this paper. The receiver is a double-conversion superheterodyne architecture. The first down-conversion is accomplished by a self-oscillating 3X subharmonic mixer frontend, and the second down-conversion is performed by a Gilbert-cell mixer and an LO. The receiver is co-designed and integrated with a 4-element loop antenna array. By mixing an RF input signal at 312 GHz with the 3rd harmonic of the 96 GHz LO, the first IF of 24 GHz is produced (fIF1=fRF-3fLO1). The second LO is at frequency of 22.3 GHz, and the second IF is 1.7 GHz (fIF2=fIF1-fLO2). The antenna array receiver exhibits a measured conversion loss of 19 dB from 312GHz RF to 1.7GHz IF, and has a -3dB bandwidth of 1.2 GHz. It is implemented in 65nm CMOS. The chip occupies an area of 1.71 mm2 and consumes DC power of 110 mW.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129552349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A dual band (2G/5G) IEEE 802.11b/g/n/ac 80MHz bandwidth AMAM envelope feedback power amplifier with digital pre-distortion 双频(2G/5G) IEEE 802.11b/g/n/ac 80MHz带宽AMAM包络反馈功率放大器，带数字预失真
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337720
S. Tam, Yuan Lu, M. Nick, Yi Zhao, A. Wong, R. Winoto, Li Lin
{"title":"A dual band (2G/5G) IEEE 802.11b/g/n/ac 80MHz bandwidth AMAM envelope feedback power amplifier with digital pre-distortion","authors":"S. Tam, Yuan Lu, M. Nick, Yi Zhao, A. Wong, R. Winoto, Li Lin","doi":"10.1109/RFIC.2015.7337720","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337720","url":null,"abstract":"A dual band (2G/5G) IEEE 802.11b/g/n/ac wide-band AM-AM envelope feedback power amplifier with digital pre-distortion is demonstrated in 40nm CMOS. This architect effectively improves both EVM and spectrum mask up to 20.9dBm in 40MHz bandwidth at 2G and 17.2dBm in 80MHz bandwidth in 5G. In addition, comparing to the conventional class AB PA, the power consumption is significantly reduced by 33% at low output power (<;6dBm) and 21% at high output power (>16dBm).","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127645956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Comprehensive ESD co-design with high-speed and high-frequency ICs in 28nm CMOS: Characterization, behavioral modeling, extraction and circuit evaluation 基于28nm CMOS的高速和高频集成电路ESD综合协同设计:特性、行为建模、提取和电路评估
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337792
Fei Lu, Z. Dong, Li Wang, R. Ma, Chen Zhang, H Zhao, Albert Z. H. Wang
{"title":"Comprehensive ESD co-design with high-speed and high-frequency ICs in 28nm CMOS: Characterization, behavioral modeling, extraction and circuit evaluation","authors":"Fei Lu, Z. Dong, Li Wang, R. Ma, Chen Zhang, H Zhao, Albert Z. H. Wang","doi":"10.1109/RFIC.2015.7337792","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337792","url":null,"abstract":"This paper reports a comprehensive electrostatic discharge (ESD) protection circuit co-design and analysis approach for high-frequency and high-speed ICs. Implemented in a 28nm CMOS, the ESD co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, parasitic ESD parameter extraction and ESD circuit evaluation for up to 40Gbps I/O circuits. This practical ESD co-design technique can be applied to high-performance, high-frequency and high-speed ICs.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A +2.3dBm 124–158GHz Class-C frequency quadrupler with folded-transformer based multi-phase driving A +2.3dBm 124-158GHz c类四频器，基于折叠式变压器的多相驱动
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2015-05-17 DOI: 10.1109/RFIC.2015.7337755
T. Chi, J. Papapolymerou, Hua Wang
{"title":"A +2.3dBm 124–158GHz Class-C frequency quadrupler with folded-transformer based multi-phase driving","authors":"T. Chi, J. Papapolymerou, Hua Wang","doi":"10.1109/RFIC.2015.7337755","DOIUrl":"https://doi.org/10.1109/RFIC.2015.7337755","url":null,"abstract":"This paper presents a D-band frequency quadrupler from 124GHz to 158GHz. The design leverages a folded-transformer based passive network to generate high-quality and broadband differential quadrature driving signals with low loss for the input tone centered at 35GHz. Then, the four-phase signals drive the 1st-stage frequency doublers to yield fully differential signals at the 2nd harmonic frequency (70GHz), which feed another push-push frequency doubler and generate the desired 4th harmonic output at 140GHz. The push-push doublers are designed based on 2nd harmonic load-pull with Class-C operation for optimized output power and efficiency. The quadrupler is implemented in a 32nm CMOS SOI process occupying only 530μm-by-550μm. It achieves the state-of-the-art output power of +2.3dBm, a peak DC-to-RF efficiency of 5.3%, and the best reported -3dB bandwidth of 24% at D-band under 1.1V supply.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133563905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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