A +2.3dBm 124-158GHz c类四频器,基于折叠式变压器的多相驱动

T. Chi, J. Papapolymerou, Hua Wang
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引用次数: 23

摘要

本文设计了一种d波段124GHz ~ 158GHz频率四倍器。该设计利用基于折叠变压器的无源网络,以35GHz为中心的输入音调产生低损耗的高质量宽带差分正交驱动信号。然后,四相信号驱动第一级倍频器产生2次谐波(70GHz)的全差分信号,该信号馈送另一个推推式倍频器,并在140GHz产生所需的4次谐波输出。推-推倍增器基于二次谐波负载-拉力设计,c级运行,优化输出功率和效率。该四倍频器采用32nm CMOS SOI工艺,仅占用530μm × 550μm。它实现了+2.3dBm的最先进输出功率,5.3%的峰值dc - rf效率,以及在1.1V电源下d频段-3dB 24%的最佳带宽。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A +2.3dBm 124–158GHz Class-C frequency quadrupler with folded-transformer based multi-phase driving
This paper presents a D-band frequency quadrupler from 124GHz to 158GHz. The design leverages a folded-transformer based passive network to generate high-quality and broadband differential quadrature driving signals with low loss for the input tone centered at 35GHz. Then, the four-phase signals drive the 1st-stage frequency doublers to yield fully differential signals at the 2nd harmonic frequency (70GHz), which feed another push-push frequency doubler and generate the desired 4th harmonic output at 140GHz. The push-push doublers are designed based on 2nd harmonic load-pull with Class-C operation for optimized output power and efficiency. The quadrupler is implemented in a 32nm CMOS SOI process occupying only 530μm-by-550μm. It achieves the state-of-the-art output power of +2.3dBm, a peak DC-to-RF efficiency of 5.3%, and the best reported -3dB bandwidth of 24% at D-band under 1.1V supply.
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