{"title":"A +2.3dBm 124–158GHz Class-C frequency quadrupler with folded-transformer based multi-phase driving","authors":"T. Chi, J. Papapolymerou, Hua Wang","doi":"10.1109/RFIC.2015.7337755","DOIUrl":null,"url":null,"abstract":"This paper presents a D-band frequency quadrupler from 124GHz to 158GHz. The design leverages a folded-transformer based passive network to generate high-quality and broadband differential quadrature driving signals with low loss for the input tone centered at 35GHz. Then, the four-phase signals drive the 1st-stage frequency doublers to yield fully differential signals at the 2nd harmonic frequency (70GHz), which feed another push-push frequency doubler and generate the desired 4th harmonic output at 140GHz. The push-push doublers are designed based on 2nd harmonic load-pull with Class-C operation for optimized output power and efficiency. The quadrupler is implemented in a 32nm CMOS SOI process occupying only 530μm-by-550μm. It achieves the state-of-the-art output power of +2.3dBm, a peak DC-to-RF efficiency of 5.3%, and the best reported -3dB bandwidth of 24% at D-band under 1.1V supply.","PeriodicalId":121490,"journal":{"name":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2015.7337755","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23
Abstract
This paper presents a D-band frequency quadrupler from 124GHz to 158GHz. The design leverages a folded-transformer based passive network to generate high-quality and broadband differential quadrature driving signals with low loss for the input tone centered at 35GHz. Then, the four-phase signals drive the 1st-stage frequency doublers to yield fully differential signals at the 2nd harmonic frequency (70GHz), which feed another push-push frequency doubler and generate the desired 4th harmonic output at 140GHz. The push-push doublers are designed based on 2nd harmonic load-pull with Class-C operation for optimized output power and efficiency. The quadrupler is implemented in a 32nm CMOS SOI process occupying only 530μm-by-550μm. It achieves the state-of-the-art output power of +2.3dBm, a peak DC-to-RF efficiency of 5.3%, and the best reported -3dB bandwidth of 24% at D-band under 1.1V supply.