Fei Lu, Z. Dong, Li Wang, R. Ma, Chen Zhang, H Zhao, Albert Z. H. Wang
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Comprehensive ESD co-design with high-speed and high-frequency ICs in 28nm CMOS: Characterization, behavioral modeling, extraction and circuit evaluation
This paper reports a comprehensive electrostatic discharge (ESD) protection circuit co-design and analysis approach for high-frequency and high-speed ICs. Implemented in a 28nm CMOS, the ESD co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, parasitic ESD parameter extraction and ESD circuit evaluation for up to 40Gbps I/O circuits. This practical ESD co-design technique can be applied to high-performance, high-frequency and high-speed ICs.
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