A 54–84 GHz CMOS SPST switch with 35 dB isolation

Abstract

This paper presents a hybrid design based, CMOS millimeter-wave (mm-wave) single-polar single-throw (SPST) switch. The circuit design starts from the analysis and optimization of a distributed structure, while implemented using coupled lump elements for performance improvement and area-efficient layout. Moreover, a specific bias scheme is used to further decrease insertion loss by more than 0.5 dB. This SPST switch achieves higher than 35 dB isolation over an ultra-wide frequency range, from 54 GHz to 84 GHz, a minimum 1.7 dB insertion loss, and <;-10 dB return loss with 0.012 mm2 chip area in 65 nm CMOS. This design achieves more than 10 dB enhancement of isolation by comparing with state-of-the-arts while maintaining similar insertion loss.