具有高调谐范围和低相位噪声的c类自混频vco结构,适用于毫米波应用

A. H. M. Shirazi, Amir Nikpaik, Reza Molavi, S. Mirabbasi, S. Shekhar
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引用次数: 11

摘要

在毫米波压控振荡器(VCO)中同时实现高调谐范围和低相位噪声一直是一个严峻的设计挑战。我们的架构,在这里称为自混合VCO (SMV),利用c类推-推式VCO拓扑产生第一(f0)和第二(2f0)谐波,然后将它们混合在一起,以获得所需的第三谐波(3f0)分量。与工作在3f0 mm波段的基模VCO相比,SMV架构具有更优越的频率调谐范围(FTR)和相位噪声(PN)性能。c类拓扑通过提高二次谐波含量来提高混频效率,降低寄生电容,降低相位噪声。采用0.13 μm CMOS工艺设计并实现了52.8 ~ 62.5 GHz的SMV原型。测量结果显示,在1 MHz偏置时,FTR为16.8%,PN为-100.57 dBc/Hz,导致包含FTR的品质因数(fmt)为-190.85 dBc/Hz,同时从1.2 V电源电压消耗7.6 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Class-C self-mixing-VCO architecture with high tuning-range and low phase-noise for mm-wave applications
Achieving high tuning-range and low phase-noise simultaneously in mm-wave voltage-controlled oscillators (VCO) has been a severe design challenge. Our architecture, referred herein as a self-mixing VCO (SMV), utilizes a Class-C push-push VCO topology to generate the first (f0) and second harmonics (2f0) and then mixes them together to obtain the desired third harmonic (3f0) component. Compared to a fundamental-mode VCO operating at 3f0 in mm-wave band, the SMV architecture achieves superior frequency tuning range (FTR) and phase-noise (PN) performance. A Class-C topology enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance and reduces phase noise. A 52.8-to-62.5 GHz SMV prototype is designed and implemented in a 0.13-μm CMOS process. Measurement results show an FTR of 16.8% together with a PN of -100.57 dBc/Hz at 1 MHz offset - resulting in an FTR-inclusive figure-of-merit (FOMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply voltage.
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