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ESSDERC 2008 - 38th European Solid-State Device Research Conference最新文献

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N-MOSFETs with inversion-layer source/drain extensions formed by cesium segregation at SiO2/Si interfaces 在SiO2/Si界面上铯偏析形成反向源/漏扩展的n- mosfet
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681767
K. Kimoto, T. Tada, T. Kanayama
{"title":"N-MOSFETs with inversion-layer source/drain extensions formed by cesium segregation at SiO2/Si interfaces","authors":"K. Kimoto, T. Tada, T. Kanayama","doi":"10.1109/ESSDERC.2008.4681767","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681767","url":null,"abstract":"We fabricated a novel type MOSFET with inversion layer source/drain extensions formed by Cs implantation and segregation at SiO2/Si interfaces beside the gate and demonstrate that it has significant immunity to short channel effect, gate induced drain leakage, and transient enhanced diffusion of channel boron impurities, compared to conventional MOSFETs. The stability of Cs in the device is also confirmed by bias-temperature-stress measurements.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122186491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Poly-Si stripe TFTs by grain-boundary controlled crystallization of amorphous-Si 晶界控制非晶硅晶化的多晶硅条纹tft
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681705
I. Brunets, J. Holleman, A. Kovalgin, J. Schmitz
{"title":"Poly-Si stripe TFTs by grain-boundary controlled crystallization of amorphous-Si","authors":"I. Brunets, J. Holleman, A. Kovalgin, J. Schmitz","doi":"10.1109/ESSDERC.2008.4681705","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681705","url":null,"abstract":"In this work, we fabricated high-performance P- and N-channel poly-Si TFTs with 16-nm gate dielectric (ALD Al2O3) at temperatures not exceeding 550degC. Using preformed a-Si lines, the grain boundaries formed during laser crystallization were predominantly location-controlled. A diode-pumped Yb:YAG thin disk green laser was used for crystallization and dopant activation. The film crystallinity was characterized with electron backscatter diffraction (EBSD). The sheet resistance of the crystallized films was studied as a function of the laser treatment energy, the location, and the orientation. The realized TFTs exhibited a field-effect mobility of 51.5 cm2/Vs and 61.9 cm2/Vs, and a subthreshold swing of 0.14 and 0.16 V/decade for p- and n-channel devices, respectively.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125708913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The future of high-performance CMOS: Trends and requirements 高性能CMOS的未来:趋势和要求
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681693
A. Khakifirooz, D. Antoniadis
{"title":"The future of high-performance CMOS: Trends and requirements","authors":"A. Khakifirooz, D. Antoniadis","doi":"10.1109/ESSDERC.2008.4681693","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681693","url":null,"abstract":"Intrinsic MOSFET time delay is examined as a function of scaling of high-performance CMOS technology. An analytical expression is used to calculate delay from physically meaningful transistor characteristics, which are either obtained from the literature or projected forward. The key performance parameter is the calculated virtual-source carrier velocity in the channel which is shown to be responsible for the historical decrease of transistor delay with scaling. Forward projection of transistor delay is based on an optimistic scaling scenario with realistic assumptions about device geometry, electrostatic integrity, and parasitics. It is shown that from the 32-nm CMOS generation onward the intrinsic transistor performance will not improve unless parasitic capacitances are significantly reduced. Finally, characteristics of performance scaling under localized circuit power density constraints are examined.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121068380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Fully self-consistent k · p solver and Monte Carlo simulator for hole inversion layers 全自洽k·p求解器和蒙特卡罗模拟孔逆温层
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681746
L. Donetti, F. Gámiz, A. Godoy, N. Rodriguez
{"title":"Fully self-consistent k · p solver and Monte Carlo simulator for hole inversion layers","authors":"L. Donetti, F. Gámiz, A. Godoy, N. Rodriguez","doi":"10.1109/ESSDERC.2008.4681746","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681746","url":null,"abstract":"We develop a fully self-consistent solver for the six-band k middot p Schrodinger and Poisson equations which enables us to compute the potential, charge distribution and subband energy in Si and Ge hole inversion layers for arbitrary substrate orientations, for both bulk and multigate MOSFETs. The results for the valence subband structure are used in a simplex Monte Carlo simulator to evaluate the low-field mobility. The results obtained in the case of bulk Si devices are compared with the universal mobility curves and a very good agreement is found.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Reduction of the dark-current in carbon nanotube photo-detectors 碳纳米管光电探测器中暗电流的减小
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681736
M. Pourfath, H. Kosina, S. Selberherr
{"title":"Reduction of the dark-current in carbon nanotube photo-detectors","authors":"M. Pourfath, H. Kosina, S. Selberherr","doi":"10.1109/ESSDERC.2008.4681736","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681736","url":null,"abstract":"Carbon nanotubes have been considered in recent years for future opto-electronic applications because of their direct band-gap and the tunability of the band-gap with the CNT diameter. The performance of infra-red photo-detectors based on carbon nanotube field-effect transistors is analyzed, using the non-equilibrium Greenpsilas function formalism. The relatively low ratio of the photo-current to the dark current limits the performance of such devices.We show that by employing a double gate structure this ratio can be significantly increased.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"408 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116516192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wireless driven EWOD technology for a MEMS pond skater 用于MEMS池塘滑板的无线驱动EWOD技术
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681759
Y. Mita, Yifan Li, M. Kubota, W. Parkes, L. Haworth, B. Flynn, J. Terry, T. Tang, A. D. Ruthven, S. Smith, A. Walton
{"title":"Wireless driven EWOD technology for a MEMS pond skater","authors":"Y. Mita, Yifan Li, M. Kubota, W. Parkes, L. Haworth, B. Flynn, J. Terry, T. Tang, A. D. Ruthven, S. Smith, A. Walton","doi":"10.1109/ESSDERC.2008.4681759","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681759","url":null,"abstract":"A silicon swimming robot or pond skating device has been demonstrated. It floats on liquid surfaces using surface tension and is capable of movement using electrowetting on dielectric (EWOD) based propulsion. Its dimensions are 6 times 9 mm with a thickness of 380 mum. The driving mechanism involves the trapping of air bubbles within the liquid onto the hydrophobic surface of the device with the subsequent ejection using a recently reported Ta2O5 EWOD technology. The required driving voltage of ~15 V is low enough for RF power transmission, thus providing wire-free movement. A wired version has been measured to move 1.35 mm in 168 ms (a speed of 8 mm s-1). This low-voltage EWOD device, fabricated using a CMOS compatible process, is believed to be the worldpsilas smallest swimming MEMS device that has no mechanical moving parts. The paper also reports results of EWOD droplet operation driven by wireless power transmission and demonstrates that such a wireless design can be successfully mounted on a floating EWOD device.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133056438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs si厚度对si钝化Ge pmosfet界面和器件性能的影响
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681718
K. Martens, J. Mitard, B. de Jaeger, M. Meuris, H. Maes, G. Groeseneken, F. Minucci, F. Crupi
{"title":"Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs","authors":"K. Martens, J. Mitard, B. de Jaeger, M. Meuris, H. Maes, G. Groeseneken, F. Minucci, F. Crupi","doi":"10.1109/ESSDERC.2008.4681718","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681718","url":null,"abstract":"The semiconductor-dielectric interface passivation of Ge pMOSFETs with an epitaxially grown Si-layer is studied by means of the full conductance technique. This technique resolves several issues which occur for alternative MOS-interfaces when using the dasiaclassicalpsila conductance technique. The observed mobility behavior as a function of Si-passivation thickness can be explained by the observed variation in interface state density. Observed threshold voltage shifts as a function of Si-passivation thickness can also be linked to the variation in interface state density with thickness.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Impact of strain on LER variability in bulk MOSFETs 应变对体mosfet中LER变异性的影响
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681730
Xingsheng Wang, S. Roy, A. Asenov
{"title":"Impact of strain on LER variability in bulk MOSFETs","authors":"Xingsheng Wang, S. Roy, A. Asenov","doi":"10.1109/ESSDERC.2008.4681730","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681730","url":null,"abstract":"This paper presents the first comprehensive three-dimensional (3D) simulation results of modern strained nMOSFETs under the influence of statistical variability, induced by gate line edge roughness (LER). The focus is the impact of strain on the LER induced variability. Stress engineering is introduced and its effects are explored. New detailed results concerning strain variability induced by LER in the channel are demonstrated, and further strain enhanced variability is captured statistically. Finally, the effects of different LER magnitude on strained devices are investigated.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126483855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improved sub-threshold slope in RF vertical MOSFETS using a frame gate architecture 利用框架栅极结构改善射频垂直mosfet的亚阈值斜率
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681707
M. Hakim, T. Uchino, W. R-White, P. Ashburn, L. Tan, O. Buiu, S. Hall
{"title":"Improved sub-threshold slope in RF vertical MOSFETS using a frame gate architecture","authors":"M. Hakim, T. Uchino, W. R-White, P. Ashburn, L. Tan, O. Buiu, S. Hall","doi":"10.1109/ESSDERC.2008.4681707","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681707","url":null,"abstract":"We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub-threshold slope and DIBL. The frame gate vertical MOSFETs show near ideal sub-threshold slopes of 70-80 mV/decade and DIBL of 30-35 mV/V in a 100 nm gate length nMOS device. In contrast, the control vertical MOSFETs without the frame gate exhibit sub-threshold slopes of 110 to 140 mV/decade and DIBL of 100 to 280 mV/V. This improved sub-threshold slope is explained by the elimination of etch damage during gate etch.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124415381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FinFET stress engineering using 3D mechanical stress and 2D Monte Carlo device simulation 采用三维机械应力和二维蒙特卡罗器件模拟的FinFET应力工程
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681725
F. M. Bufler, L. Sponton, A. Erlebach
{"title":"FinFET stress engineering using 3D mechanical stress and 2D Monte Carlo device simulation","authors":"F. M. Bufler, L. Sponton, A. Erlebach","doi":"10.1109/ESSDERC.2008.4681725","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681725","url":null,"abstract":"A simulation methodology for FinFET stress and crystallographic orientation engineering is introduced and applied to tall scaled p- and n-type FinFETs with strained nitride layers on (001) wafers. The methodology consists of combining 3D mechanical stress simulation with 2D Monte Carlo device simulation where an averaged channel stress tensor is used. 50 nm down to 10 nm gate-length p- and n-type FinFETs with (110)/110 surface and channel orientation as well as (010)/100 n-type FinFETs are simulated with compressively and tensile strained cap layers, respectively, where liner stress values from 0.8 to 2.0 GPa are considered. Stress-induced Idsat gains in the range of 10 to 35% are found for pFinFETs with increasing tendency upon scaling, while the nFinFETs involve gains between 5 and 15% decreasing for smaller gate lengths with the highest absolute current being obtained for the 100 channel direction.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132587986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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