ESSDERC 2008 - 38th European Solid-State Device Research Conference最新文献

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Integration of resistive switching NiO in small via structures from localized oxidation of nickel metallic layer 镍金属层局部氧化在小通孔结构中集成阻性开关NiO
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681737
L. Courtade, C. Turquat, J. Lisoni, L. Goux, D. Wouters, D. Deleruyelle, C. Muller
{"title":"Integration of resistive switching NiO in small via structures from localized oxidation of nickel metallic layer","authors":"L. Courtade, C. Turquat, J. Lisoni, L. Goux, D. Wouters, D. Deleruyelle, C. Muller","doi":"10.1109/ESSDERC.2008.4681737","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681737","url":null,"abstract":"Conventional memories approaching their scaling limit, reversible resistance switching effects attract considerable attention because of the potential for high density non volatile memory devices. These resistive switching phenomena have been reported in many simple transition metal oxide films such as TiO2 or NiO deposited by standard sputtering techniques. This paper is investigating the feasibility of emerging resistive-switching stacks enabling integration of the memory element in interconnect structures resulting in very small memory cells. Indeed, we have developed innovative process steps leading to localized formation of bi-stable NiO at the bottom of via structures. Thickness-controlled NiO layers were formed from the partial oxidation of blanket Ni metallic layer through via holes opened in SiO2. Reversible and repetitive switching was demonstrated on arrays of vias with diameter down to 150 nm. Besides, encouraging reliability performances in terms of endurance and retention were obtained.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129458474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Atomically flat gate insulator/silicon (100) interface formation introducing high mobility, ultra-low noise, and small characteristics variation CMOSFET 原子平栅绝缘子/硅(100)界面形成引入了高迁移率,超低噪声和小特性变化的CMOSFET
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-09-01 DOI: 10.1109/ESSDERC.2008.4681704
R. Kuroda, A. Teramoto, T. Suwa, R. Hasebe, X. Li, M. Konda, S. Sugawa, T. Ohmi
{"title":"Atomically flat gate insulator/silicon (100) interface formation introducing high mobility, ultra-low noise, and small characteristics variation CMOSFET","authors":"R. Kuroda, A. Teramoto, T. Suwa, R. Hasebe, X. Li, M. Konda, S. Sugawa, T. Ohmi","doi":"10.1109/ESSDERC.2008.4681704","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681704","url":null,"abstract":"Atomically flat silicon surface constructed with atomic terraces and steps is realized by pure argon ambience annealing at 1200degC on (100) crystal orientation large diameter wafers with precisely controlled tilt angle. Only the radical reaction based insulator formation technology such as oxidation utilizing oxygen radicals carried out at low temperature (400degC) can preserve the atomically flatness at the gate insulator film/silicon interface. CMOSFET having the atomically flat interface exhibit extremely lower 1/f noise and higher mobility characteristics with smaller electrical variation than those of CMOSFETs fabricated by the conventional technologies.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127883937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Solving issues of integrated circuits by 3D-stacking Meeting with the era of power, integrity attackers and NRE explosion and a bit of future 用3d堆叠解决集成电路问题,与权力时代、完整性攻击者、NRE爆炸和一点未来相遇
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 1900-01-01 DOI: 10.1109/esscirc.2008.4681784
T. Sakurai
{"title":"Solving issues of integrated circuits by 3D-stacking Meeting with the era of power, integrity attackers and NRE explosion and a bit of future","authors":"T. Sakurai","doi":"10.1109/esscirc.2008.4681784","DOIUrl":"https://doi.org/10.1109/esscirc.2008.4681784","url":null,"abstract":"In the foreseeable future, VLSI design will meet a couple of explosions: explosion of power, explosion of integrity attackers including power integrity and signal integrity and explosion of NRE (non-recurring engineering cost). A remedy for power explosion and explosion of integrity attackers lies in ldquovoltage engineeringrdquo. A remedy for the NRE explosion is to reduce the number of developments and sell tens of millions of chips with a fixed design. 3D-stacked LSI approach may embody such possibility. The talk will cover example of the solutions based on 3D-stacking. Several new circuit technologies for voltage engineering, including distributed DC-DC converters and proximity interfaces are described to enable 3-D stacking of chips to build high-performance yet low-power electronics systems. On the other extreme of the silicon VLSIpsilas which stay as small as a centimeter square, a new domain of electronics called large-area integrated circuit as large as meters is waiting to open up a new continent of applications in the era of ubiquitous electronics. One of the implementations of the large-area electronics is based on organic transistors. The talk will provide perspectives of the organic circuit design taking E-skin, sheet-type scanner, Braille display and wireless power transmission and communication sheet as examples.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122946938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Printed electronics for low-cost electronic systems: Technology status and application development 用于低成本电子系统的印刷电子:技术现状和应用发展
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 1900-01-01 DOI: 10.1109/essderc.2008.4681691
V. Subramanian, Josephine B. Chang, Alejandro de la Fuente Vornbrock, Daniel C. Huang, Lakshminarayan K. Jagannathan, F. Liao, B. Mattis, S. Molesa, D. Redinger, D. Soltman, S. Volkman, Qintao Zhang
{"title":"Printed electronics for low-cost electronic systems: Technology status and application development","authors":"V. Subramanian, Josephine B. Chang, Alejandro de la Fuente Vornbrock, Daniel C. Huang, Lakshminarayan K. Jagannathan, F. Liao, B. Mattis, S. Molesa, D. Redinger, D. Soltman, S. Volkman, Qintao Zhang","doi":"10.1109/essderc.2008.4681691","DOIUrl":"https://doi.org/10.1109/essderc.2008.4681691","url":null,"abstract":"In recent years, printing has received substantial interest as a technique for realizing low cost, large area electronic systems. Printing allows the use of purely additive processing, thus lowering process complexity and material usage. Coupled with the use of low-cost substrates such as plastic, metal foils, etc., it is expected that printed electronics will enable the realization of a wide range of easily deployable electronic systems, including displays, sensors, and RFID tags. We review our work on the development of technologies and applications for printed electronics. By combining synthetically derived inorganic nanoparticles and organic materials, we have realized a range of printable electronic “inks”, and used these to demonstrate printed passive components, multilayer interconnection, diodes, transistors, memories, batteries, and various types of gas and biosensors. By exploiting the ability of printing to cheaply allow for the integration of diverse functionalities and materials onto the same substrate, therefore, it is possible to realize printed systems that exploit the advantages of printing while working around the disadvantages of the same.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126444644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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