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Double gate movable body Micro-Electro-Mechanical FET as hysteretic switch: Application to data transmission systems 作为滞回开关的双栅可动体微机电场效应管:在数据传输系统中的应用
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681758
D. Grogg, C. Meinen, D. Tsamados, H. Tekin, M. Kayal, A. Ionescu
{"title":"Double gate movable body Micro-Electro-Mechanical FET as hysteretic switch: Application to data transmission systems","authors":"D. Grogg, C. Meinen, D. Tsamados, H. Tekin, M. Kayal, A. Ionescu","doi":"10.1109/ESSDERC.2008.4681758","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681758","url":null,"abstract":"This paper reports on the fabrication, experimental characterization and data transmission application of a double-gate movable body FET. As its name suggests, the proposed movable-body Micro-Electro-Mechanical FET (MB-MEMFET) is a hybrid MEMS-semiconductor device that, in contrast with previously reported Suspended-Gate MOSFET, has a movable body separated by nano-size air gaps from two lateral fixed gates. We report here on the unique abrupt hysteretic characteristic of MB-MEMFET, which for our design offer reproducibility after intense cycling and, due to double gate architecture, a multi-level tunable hysteresis. Based on the ID-VG hysteretic behavior of the new hybrid device we report for the first time a FSK circuit exploiting oscillation at two selectable frequencies (26 kHz and 14 kHz) used to transmit numerical data, which demonstrates the potential of the MB-MEMFET for applications in data transmission systems.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123284093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High mobility Ge and III–V materials and novel device structures for high performance nanoscale MOSFETS 高性能纳米级mosfet的高迁移率Ge和III-V材料和新型器件结构
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681694
T. Krishnamohan, K. Saraswat
{"title":"High mobility Ge and III–V materials and novel device structures for high performance nanoscale MOSFETS","authors":"T. Krishnamohan, K. Saraswat","doi":"10.1109/ESSDERC.2008.4681694","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681694","url":null,"abstract":"In order to continue the scaling of silicon-based CMOS and maintain the historic progress in information processing and transmission, innovative device structures and new materials have to be created. A channel material with high mobility and therefore high injection velocity can increase on current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs and increasing the strain provides a viable solution to scaling. However, looking into future scaling of nanoscale MOSFETs it becomes important to look at higher mobility materials, like Ge and III-V materials together with innovative device structures and strain, which may perform better than even very highly strained Si. For both Ge and III-V devices problems of leakage need to be solved. Novel heterostructure quantum-well (QW) FETs will be needed to exploit the promised advantages of Ge and III-V based devices.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"36 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114042663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Evaluation of intrinsic parameter fluctuations on 45, 32 and 22nm technology node LP N-MOSFETs 45、32和22nm工艺节点LP n - mosfet的内在参数波动评估
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681695
B. Cheng, S. Roy, A. R. Brown, C. Millar, A. Asenov
{"title":"Evaluation of intrinsic parameter fluctuations on 45, 32 and 22nm technology node LP N-MOSFETs","authors":"B. Cheng, S. Roy, A. R. Brown, C. Millar, A. Asenov","doi":"10.1109/ESSDERC.2008.4681695","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681695","url":null,"abstract":"The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115306998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Influence of gate underlap in AM and IM MuGFETs 栅极搭接对AM和IM微场效应管的影响
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681742
Chi-Woo Lee, A. Afzalian, R. Yan, N. Dehdashti, W. Xiong, J. Colinge
{"title":"Influence of gate underlap in AM and IM MuGFETs","authors":"Chi-Woo Lee, A. Afzalian, R. Yan, N. Dehdashti, W. Xiong, J. Colinge","doi":"10.1109/ESSDERC.2008.4681742","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681742","url":null,"abstract":"The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode (AM) devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode (IM) FETs.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124570672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved analog performance of strained Si n-MOSFETs on thin SiGe strained relaxed buffers 应变Si - n- mosfet在薄SiGe应变松弛缓冲器上模拟性能的改善
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681708
O. Alatise, Kelvin S. K. Kwa, S. Olsen, A. O'Neill
{"title":"Improved analog performance of strained Si n-MOSFETs on thin SiGe strained relaxed buffers","authors":"O. Alatise, Kelvin S. K. Kwa, S. Olsen, A. O'Neill","doi":"10.1109/ESSDERC.2008.4681708","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681708","url":null,"abstract":"Strained Si/SiGe devices offer a route to high speed digital devices. Analog design trade-offs can also be improved using strained Si if device self-heating can be controlled; strained Si is generated using a strain relaxed buffer (SRB) of SiGe which has a lower thermal conductivity compared with bulk Si. In this work the impact of the SiGe SRB thickness on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self heating at high power levels leads to negative self gain and anomalous circuit behavior in terms of nonlinear phase shifts. By using ac and dc measurements we show that by reducing the SRB thickness self-heating effects are significantly lower and the analog design space is improved. The range of gate voltages that leverage positive self gain in 100 nm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by 100% compared with strained Si devices fabricated on conventional SRBs 4 mum thick. Guidelines for the maximum SRB thicknesses required to obtain positive self gain for highly scaled technology generations where self-heating effects increase are presented. For a 22 nm technology node, the SRB thickness should not exceed 20 nm for 1.5 V drain voltage and gate overdrive. The thin SRB is grown using a C-layer and does not compromise any aspect of device performance.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130600187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Process-induced SOI strain via sacrificial Ge-Si 牺牲锗硅的过程诱导SOI应变
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681756
D. Connelly, P. Clifton
{"title":"Process-induced SOI strain via sacrificial Ge-Si","authors":"D. Connelly, P. Clifton","doi":"10.1109/ESSDERC.2008.4681756","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681756","url":null,"abstract":"We present here, for the first time, a method of introducing strain into Si, for example ultra-thin SOI, with a sacrificial strained Ge<sub>x</sub>Si<sub>1-x</sub> layers. Etching proximate trenches into the Ge<sub>x</sub>Si<sub>1-x</sub>-Si stack causes the stack to relax, transferring strain from the surface Ge<sub>x</sub>Si<sub>1-x</sub> into the buried Si. Filling the trenches locks the strain in place, where it remains after the Ge<sub>x</sub>Si<sub>1-x</sub> is removed. This method can be combined with more conventional stress engineering, such as strained trench fills, strained source/drain epitaxy, or strained overlayers.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133508921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the role of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories HTO/Al2O3双层阻挡氧化物在氮阱非易失性存储器中的作用
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681713
M. Bocquet, G. Molas, L. Perniola, X. Garros, J. Buckley, M. Gely, J. Colonna, H. Grampeix, F. Martin, V. Vidal, A. Toffoli, B. De Salvo, S. Deleonibus, G. Pananakakis, G. Ghibaudo
{"title":"On the role of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories","authors":"M. Bocquet, G. Molas, L. Perniola, X. Garros, J. Buckley, M. Gely, J. Colonna, H. Grampeix, F. Martin, V. Vidal, A. Toffoli, B. De Salvo, S. Deleonibus, G. Pananakakis, G. Ghibaudo","doi":"10.1109/ESSDERC.2008.4681713","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681713","url":null,"abstract":"In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al2O3 bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed, focusing on their impact on memory performance and reliability. Then, a semi-analytical model is developed, which provides a good understanding of the physical mechanisms at the origin of program/erase characteristics.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"29 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131063279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Impact of the charge transport in the conduction band on the retention of Si-nitride based memories 导电带电荷输运对氮化硅基记忆体保留的影响
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681710
E. Vianello, F. Driussi, P. Palestri, A. Arreghini, D. Esseni, L. Selmi, N. Akil, M. van Duuren, D. Golubović
{"title":"Impact of the charge transport in the conduction band on the retention of Si-nitride based memories","authors":"E. Vianello, F. Driussi, P. Palestri, A. Arreghini, D. Esseni, L. Selmi, N. Akil, M. van Duuren, D. Golubović","doi":"10.1109/ESSDERC.2008.4681710","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681710","url":null,"abstract":"An improved model for charge injection through ONO gate stacks, that comprises carrier transport in the conduction band of the silicon nitride (Si3N4), is used to investigate the program/retention sequence of Si3N4 based (SONOS/TANOS) non volatile memories without making assumptions on the initial distribution of the trapped charge at the beginning of retention. We show that carrier transport in the Si3N4 layer impacts the spatial charge distribution and consequently several other aspects of the retention transient. The interpretation of the Arrehnius plots of the high temperature retention data, typically used to infer the trap depth from the retention activation energy is discussed. The model provides a simple explanation of the small threshold voltage increase observed during retention experiments of thick tunnel oxide ONO stacks.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133930163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Non-hysteretic punchthrough impact ionization MOS (PIMOS) transistor: Application to abrupt inverter and NDR circuits 非迟滞穿孔式冲击电离MOS晶体管:在突变逆变器和NDR电路中的应用
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681760
V. Pott, K. Moselund, A. Ionescu
{"title":"Non-hysteretic punchthrough impact ionization MOS (PIMOS) transistor: Application to abrupt inverter and NDR circuits","authors":"V. Pott, K. Moselund, A. Ionescu","doi":"10.1109/ESSDERC.2008.4681760","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681760","url":null,"abstract":"The recently proposed PIMOS transistor can offer, by appropriate operation, non-hysteretic abrupt off-on transitions due to impact ionization if the action of its parasitic bipolar transistor is minimized. This work proposes non-hysteretic abrupt inverter circuits based on <10 mV/decade room temperature current switching and a tunable negative differential resistance based on punch-through impact ionization MOS transistors (PIMOS) when parasitic bipolar action is cancelled by choosing an appropriate drain voltage. The proposed circuit architectures are compatible with silicon CMOS nodes. The very abrupt non-hysteretic inverter shows gain of the order of -100 in the transition region of the voltage transfer characteristic (VTC). The NDR circuit exhibits tunable peak-to-valley PVR values and a negative resistance in the range of hundreds of kOmega.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130329157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs CMOS兼容栅极全能垂直硅纳米线mosfet
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681762
B. Yang, K. Buddharaju, S. Teo, J. Fu, N. Singh, G. Lo, D. Kwong
{"title":"CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs","authors":"B. Yang, K. Buddharaju, S. Teo, J. Fu, N. Singh, G. Lo, D. Kwong","doi":"10.1109/ESSDERC.2008.4681762","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681762","url":null,"abstract":"We present vertical gate-all-around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50:1) vertical nanowires with diameter down to ~ 20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. n- and p-MOS devices thus fabricated with gate length ~ 120 nm to 150 nm showed excellent transistor characteristics with large drive current per wire, high Ion/Ioff ratio (~ 107), good subthreshold slope (~ 80 mV/dec) and low DIBL (~ 20 mV/ V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124236115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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