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New analysis of heavily doped boron and arsenic in shallow junctions by X-ray photoelectron spectroscopy 浅结中重掺杂硼和砷的x射线光电子能谱新分析
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681719
K. Tsutsui, M. Watanabe, Y. Nakagawa, T. Matsuda, T. Yoshida, E. Ikenaga, K. Kakushima, P. Ahmet, H. Nohira, T. Maruizumi, A. Ogura, T. Hattori, H. Iwai
{"title":"New analysis of heavily doped boron and arsenic in shallow junctions by X-ray photoelectron spectroscopy","authors":"K. Tsutsui, M. Watanabe, Y. Nakagawa, T. Matsuda, T. Yoshida, E. Ikenaga, K. Kakushima, P. Ahmet, H. Nohira, T. Maruizumi, A. Ogura, T. Hattori, H. Iwai","doi":"10.1109/ESSDERC.2008.4681719","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681719","url":null,"abstract":"Chemical bonding states of boron (B) in shallow P+/N junctions were studied by soft X-ray photoelectron spectroscopy (SXPES). The concentration profiles of B having different binding energies were successfully determined the SXPES combined with the step-by-step etching of Si substrates. The concentration profiles of B having the lowest binding energy can be assigned as activated B, which agreed quite well with those of holes determined by the Hall measurements, while those having the middle and highest binding energies must be attributed to deactivated B. Effects of the spike-RTA and flush lamp annealing (FLA) were compared regarding the concentration profiles of B and UV Raman spectroscopy. Arsenic (As) doped layers were also studied by the X-ray photoelectron spectroscopy and the two different bonding states were revealed for As atoms embedded in Si substrates.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116401158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High efficiency embedded decoupling capacitors for MCM applications 用于MCM应用的高效嵌入式去耦电容器
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681748
O. Tesson, F. Le Cornec, S. Jacqueline
{"title":"High efficiency embedded decoupling capacitors for MCM applications","authors":"O. Tesson, F. Le Cornec, S. Jacqueline","doi":"10.1109/ESSDERC.2008.4681748","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681748","url":null,"abstract":"In this paper, RF characterization results of decoupling capacitors embedded in high resistivity silicon (HRS) substrate are reported. First, an innovative 3-D architecture suitable for silicon processes is decribed. Then, RF characterization results are analyzed based on capacitance values as well as ESR (estimated serial resistance) and ESL (estimated serial inductance) extraction. Results clearly show that devices reach a very low level of impedance together with low parasitic inductance in millimeter wave domain. A predictive electrical model composed of a cascade of T elements is derived from measurements and optimised to figure-out the distributed nature of the capacitance. Correlations between measurements and simulation data are found satisfactory.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122233375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology 采用45nm多通道场效应晶体管技术的低功耗、高稳定性6T SRAM单元
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681721
O. Thomas, B. Guillaumot, T. Ernst, B. Cousin, O. Rozeau
{"title":"A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology","authors":"O. Thomas, B. Guillaumot, T. Ernst, B. Cousin, O. Rozeau","doi":"10.1109/ESSDERC.2008.4681721","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681721","url":null,"abstract":"This paper presents an innovative 3D CMOS 6T SRAM cell design in multi-channel (MC) FET technology by well adapting the number of channels per device. A simulation model for the 45 nm MCFET has been developed based on silicon measurements. The electrical results validated by simulations, exhibit more than 25% power dissipation reduction and 17% cell stability improvement for the same area and read access time, when compared with a standard CMOS 6T SRAM cell designed in 2D.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128746781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Stress enhancement concept on replacement gate technology with top-cut stress liner for nFETs 非场效应管顶切应力衬垫替代栅技术的应力增强概念
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681727
S. Yamakawa, S. Mayuzumi, Y. Tateshita, H. Wakabayashi, H. Ansai
{"title":"Stress enhancement concept on replacement gate technology with top-cut stress liner for nFETs","authors":"S. Yamakawa, S. Mayuzumi, Y. Tateshita, H. Wakabayashi, H. Ansai","doi":"10.1109/ESSDERC.2008.4681727","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681727","url":null,"abstract":"Electron mobility enhancement using a top-cut stress liner and the replacement gate process is demonstrated and the concept of stress localization is proposed, for the first time. Eliminating a dummy gate after tensile stress liner formation enhances lateral stress at the channel region and achieves good mobility improvement. A detailed analysis using stress and mobility calculation based on a band model is performed. It is found that this new mobility enhancement technology has potential advantages in the shorter gate length region in comparison with the conventional gate-first process.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126505858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A mobility extraction method for 3D multichannel devices 一种三维多通道器件的移动度提取方法
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681740
C. Dupré, T. Ernst, É. Bernard, B. Guillaumot, N. Vulliet, P. Coronel, T. Skotnicki, S. Cristoloveanu, G. Ghibaudo, S. Deleonibus
{"title":"A mobility extraction method for 3D multichannel devices","authors":"C. Dupré, T. Ernst, É. Bernard, B. Guillaumot, N. Vulliet, P. Coronel, T. Skotnicki, S. Cristoloveanu, G. Ghibaudo, S. Deleonibus","doi":"10.1109/ESSDERC.2008.4681740","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681740","url":null,"abstract":"A novel parameter extraction method is proposed to dissociate the current contributions of each channel of highly performing Multi-Channel CMOS Low Standby Power architecture. It is shown that the very high ION/IOFF ratio (NMOS: 2.27 mA/mum for 16 pA/mum PMOS 1.32 mA/mum for 16 pA/mum) obtained experimentally benefits from good short-channel mobility values of each type of channel despite a limited degradation of the GAA mobility value.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"13 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134106791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Overview and future challenges of Floating Body RAM (FBRAM) technology for 32nm technology node and beyond 32纳米及以上节点浮动体内存(FBRAM)技术概述及未来挑战
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681692
T. Hamamoto, T. Ohsawa
{"title":"Overview and future challenges of Floating Body RAM (FBRAM) technology for 32nm technology node and beyond","authors":"T. Hamamoto, T. Ohsawa","doi":"10.1109/ESSDERC.2008.4681692","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681692","url":null,"abstract":"Floating body cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128 Mb floating body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single cell (1Cell/Bit) operation, are reviewed. Based on the experimental results, the scalability of FBC is also discussed.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130937163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On the RESET-SET transition in Phase Change Memories 相变存储器中RESET-SET转换的研究
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681723
G. Puzzilli, F. Irrera, A. Padovani, P. Pavan, L. Larcher, A. Arya, V. della Marca, A. Pirovano
{"title":"On the RESET-SET transition in Phase Change Memories","authors":"G. Puzzilli, F. Irrera, A. Padovani, P. Pavan, L. Larcher, A. Arya, V. della Marca, A. Pirovano","doi":"10.1109/ESSDERC.2008.4681723","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681723","url":null,"abstract":"We characterize SET operation in Phase Change Memories. A measurement procedure aiming to investigate resistance transition from amorphous to crystalline states is shown. Results give interesting insights on the crystallization process of GST material and a simple model is introduced. Crystallization process obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for an optimized design of memory cell operating conditions.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115321804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Study of Ferrocene/Silicon hybrid memories: Influence of the chemical linkers and device thermal stability 二茂铁/硅杂化存储器的研究:化学连接剂和器件热稳定性的影响
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681739
T. Pro, J. Buckley, R. Barattin, A. Calborean, M. Gely, K. Huang, G. Delapierre, F. Duclairoir, E. Jalaguier, P. Maldivi, B. De Salvo, S. Deleonibus, G. Ghibaudo
{"title":"Study of Ferrocene/Silicon hybrid memories: Influence of the chemical linkers and device thermal stability","authors":"T. Pro, J. Buckley, R. Barattin, A. Calborean, M. Gely, K. Huang, G. Delapierre, F. Duclairoir, E. Jalaguier, P. Maldivi, B. De Salvo, S. Deleonibus, G. Ghibaudo","doi":"10.1109/ESSDERC.2008.4681739","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681739","url":null,"abstract":"In this paper we propose an experimental and theoretical analysis of hybrid Ferrocene/Si memory structures. Two main aspects are studied: the influence of the chemical linker length on Ferrocene/Silicon electron transfer rate, and the thermal stability of the hybrid devices. X-Ray Photoelectron Spectroscopy was used to analyse the chemical structure of the molecular layers. Cyclic Voltammetry and impedance spectroscopy were employed to study the charge transfer dependence on the molecular linker. Impedance tests allowed us to evaluate the thermal stability of the molecular memories. The devices were submitted to different annealing temperatures and annealing times. The degradation of the molecular layer and the parasitic oxidation of the device active areas allowed us to explain results. Finally the main molecular parameters were computed through Density Functional Theory (DFT) calculations.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117037569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Micropower energy scavenging 微能量清除
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681689
P. Fiorini, I. Doms, C. Hoof, R. Vullers
{"title":"Micropower energy scavenging","authors":"P. Fiorini, I. Doms, C. Hoof, R. Vullers","doi":"10.1109/ESSDERC.2008.4681689","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681689","url":null,"abstract":"More than a decade of research in the field of thermal, motion, and vibrational energy scavenging has yielded increasing power output and smaller embodiments. Power management circuits for rectification and DC-DC conversion are becoming able to efficiently convert the power from these energy scavengers. This paper summarizes recent energy scavenging results and their power management circuits.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117200548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Pure boron-doped photodiodes: A solution for radiation detection in EUV lithography 纯掺硼光电二极管:EUV光刻中辐射检测的解决方案
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681752
F. Sarubbi, L. Nanver, T. Scholtes, S. Nihtianov, F. Scholze
{"title":"Pure boron-doped photodiodes: A solution for radiation detection in EUV lithography","authors":"F. Sarubbi, L. Nanver, T. Scholtes, S. Nihtianov, F. Scholze","doi":"10.1109/ESSDERC.2008.4681752","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681752","url":null,"abstract":"A pure boron chemical vapor deposition (CVD) technology, which forms delta-doped boron surface layers during diborane B2H6 exposure at 700degC, has been successfully used to fabricate silicon-based p+n photodiodes for radiation detection in the extreme-ultra-violet (EUV) spectral range. Outstanding electrical and optical performance has been achieved in terms of extremely low dark current (< 50 pA at reverse bias of 10 V), near theoretical responsivity (0.266 A/W at 13.5 nm wavelength), and excellent stability to high radiation doses (< 1% responsivity degradation after 0.2 MJ/cm2 exposure). Therefore, the diodes are suitable candidates for photon detection functions in the next-generation EUV lithography systems.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"61 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130949937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
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