A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology

Abstract

This paper presents an innovative 3D CMOS 6T SRAM cell design in multi-channel (MC) FET technology by well adapting the number of channels per device. A simulation model for the 45 nm MCFET has been developed based on silicon measurements. The electrical results validated by simulations, exhibit more than 25% power dissipation reduction and 17% cell stability improvement for the same area and read access time, when compared with a standard CMOS 6T SRAM cell designed in 2D.