Impact of strain on LER variability in bulk MOSFETs

Abstract

This paper presents the first comprehensive three-dimensional (3D) simulation results of modern strained nMOSFETs under the influence of statistical variability, induced by gate line edge roughness (LER). The focus is the impact of strain on the LER induced variability. Stress engineering is introduced and its effects are explored. New detailed results concerning strain variability induced by LER in the channel are demonstrated, and further strain enhanced variability is captured statistically. Finally, the effects of different LER magnitude on strained devices are investigated.