The future of high-performance CMOS: Trends and requirements

Abstract

Intrinsic MOSFET time delay is examined as a function of scaling of high-performance CMOS technology. An analytical expression is used to calculate delay from physically meaningful transistor characteristics, which are either obtained from the literature or projected forward. The key performance parameter is the calculated virtual-source carrier velocity in the channel which is shown to be responsible for the historical decrease of transistor delay with scaling. Forward projection of transistor delay is based on an optimistic scaling scenario with realistic assumptions about device geometry, electrostatic integrity, and parasitics. It is shown that from the 32-nm CMOS generation onward the intrinsic transistor performance will not improve unless parasitic capacitances are significantly reduced. Finally, characteristics of performance scaling under localized circuit power density constraints are examined.